CarolineConcatto created this revision.
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As described in: https://github.com/ARM-software/acle/pull/257
Patch by : David Sherwood <david.sherw...@arm.com>
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D151307
Files:
clang/include/clang/Basic/arm_sve.td
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_while_pn.c
clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
Index: clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
===================================================================
--- clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
+++ clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
@@ -49,6 +49,74 @@
svpsel_lane_c64(svptrue_c64(), svptrue_b64(), 0, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
}
+svcount_t test_svwhile_pn(int64_t op1, int64_t op2) {
+ svwhilege_c8(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilege_c16(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilege_c32(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilege_c64(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilegt_c8(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilegt_c16(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilegt_c32(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilegt_c64(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilehi_c8(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilehi_c16(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilehi_c32(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilehi_c64(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilehs_c8(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilehs_c16(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilehs_c32(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilehs_c64(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilele_c8(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilele_c16(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilele_c32(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilele_c64(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilelo_c8(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilelo_c16(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilelo_c32(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilelo_c64(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilels_c8(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilels_c16(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilels_c32(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilels_c64(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilelt_c8(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilelt_c16(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilelt_c32(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+ svwhilelt_c64(op1, op2, 6); // expected-error {{argument value 6 is outside the valid range [2, 4]}}
+
+ svwhilege_c8(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilege_c16(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilege_c32(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilege_c64(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilegt_c8(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilegt_c16(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilegt_c32(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilegt_c64(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilehi_c8(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilehi_c16(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilehi_c32(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilehi_c64(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilehs_c8(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilehs_c16(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilehs_c32(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilehs_c64(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilele_c8(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilele_c16(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilele_c32(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilele_c64(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilelo_c8(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilelo_c16(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilelo_c32(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilelo_c64(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilels_c8(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilels_c16(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilels_c32(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilels_c64(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilelt_c8(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilelt_c16(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilelt_c32(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+ svwhilelt_c64(op1, op2, 3); // expected-error {{argument should be a multiple of 2}}
+}
+
void test_cntp(svcount_t c) {
svcntp_c8(c, 1); // expected-error {{argument value 1 is outside the valid range [2, 4]}}
svcntp_c11(c, 1); // expected-error {{argument value 1 is outside the valid range [2, 4]}}
Index: clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_while_pn.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_while_pn.c
@@ -0,0 +1,992 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+// REQUIRES: aarch64-registered-target
+
+#include <arm_sve.h>
+
+
+// WHILEGE
+
+// CHECK-LABEL: @test_svwhilege_c8_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilege_c8_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilege_c8_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilege_c8(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilege_c8_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilege_c8_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilege_c8_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilege_c8(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilege_c16_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilege_c16_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilege_c16_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilege_c16(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilege_c16_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilege_c16_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilege_c16_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilege_c16(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilege_c32_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilege_c32_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilege_c32_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilege_c32(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilege_c32_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilege_c32_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilege_c32_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilege_c32(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilege_c64_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilege_c64_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilege_c64_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilege_c64(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilege_c64_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilege_c64_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilege.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilege_c64_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilege_c64(op1, op2, 4);
+}
+
+// WHILEGT
+
+
+// CHECK-LABEL: @test_svwhilegt_c8_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilegt_c8_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilegt_c8_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilegt_c8(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilegt_c8_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilegt_c8_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilegt_c8_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilegt_c8(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilegt_c16_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilegt_c16_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilegt_c16_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilegt_c16(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilegt_c16_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilegt_c16_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilegt_c16_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilegt_c16(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilegt_c32_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilegt_c32_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilegt_c32_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilegt_c32(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilegt_c32_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilegt_c32_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilegt_c32_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilegt_c32(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilegt_c64_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilegt_c64_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilegt_c64_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilegt_c64(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilegt_c64_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilegt_c64_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilegt.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilegt_c64_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilegt_c64(op1, op2, 4);
+}
+
+
+// WHILEHI
+
+// CHECK-LABEL: @test_svwhilehi_c8_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilehi_c8_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehi_c8_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilehi_c8(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilehi_c8_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilehi_c8_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehi_c8_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilehi_c8(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilehi_c16_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehi_c16_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehi_c16_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilehi_c16(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilehi_c16_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehi_c16_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehi_c16_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilehi_c16(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilehi_c32_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehi_c32_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehi_c32_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilehi_c32(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilehi_c32_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehi_c32_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehi_c32_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilehi_c32(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilehi_c64_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehi_c64_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehi_c64_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilehi_c64(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilehi_c64_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehi_c64_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehi.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehi_c64_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilehi_c64(op1, op2, 4);
+}
+
+
+// WHILEHS
+
+// CHECK-LABEL: @test_svwhilehs_c8_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilehs_c8_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehs_c8_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilehs_c8(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilehs_c8_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilehs_c8_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehs_c8_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilehs_c8(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilehs_c16_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehs_c16_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehs_c16_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilehs_c16(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilehs_c16_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehs_c16_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehs_c16_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilehs_c16(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilehs_c32_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehs_c32_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehs_c32_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilehs_c32(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilehs_c32_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehs_c32_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehs_c32_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilehs_c32(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilehs_c64_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehs_c64_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehs_c64_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilehs_c64(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilehs_c64_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilehs_c64_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilehs.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilehs_c64_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilehs_c64(op1, op2, 4);
+}
+
+
+// WHILELE
+
+// CHECK-LABEL: @test_svwhilele_c8_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilele_c8_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilele_c8_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilele_c8(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilele_c8_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilele_c8_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilele_c8_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilele_c8(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilele_c16_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilele_c16_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilele_c16_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilele_c16(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilele_c16_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilele_c16_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilele_c16_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilele_c16(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilele_c32_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilele_c32_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilele_c32_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilele_c32(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilele_c32_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilele_c32_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilele_c32_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilele_c32(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilele_c64_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilele_c64_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilele_c64_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilele_c64(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilele_c64_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilele_c64_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilele.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilele_c64_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilele_c64(op1, op2, 4);
+}
+
+
+// WHILELO
+
+// CHECK-LABEL: @test_svwhilelo_c8_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilelo_c8_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelo_c8_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilelo_c8(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilelo_c8_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilelo_c8_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelo_c8_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilelo_c8(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilelo_c16_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelo_c16_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelo_c16_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilelo_c16(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilelo_c16_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelo_c16_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelo_c16_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilelo_c16(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilelo_c32_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelo_c32_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelo_c32_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilelo_c32(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilelo_c32_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelo_c32_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelo_c32_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilelo_c32(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilelo_c64_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelo_c64_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelo_c64_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilelo_c64(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilelo_c64_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelo_c64_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelo_c64_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilelo_c64(op1, op2, 4);
+}
+
+
+// WHILELS
+
+// CHECK-LABEL: @test_svwhilels_c8_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilels_c8_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilels_c8_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilels_c8(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilels_c8_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilels_c8_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilels_c8_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilels_c8(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilels_c16_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilels_c16_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilels_c16_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilels_c16(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilels_c16_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilels_c16_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilels_c16_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilels_c16(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilels_c32_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilels_c32_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilels_c32_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilels_c32(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilels_c32_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilels_c32_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilels_c32_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilels_c32(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilels_c64_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilels_c64_vl2mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilels_c64_vl2(uint64_t op1, uint64_t op2)
+{
+ return svwhilels_c64(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilels_c64_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilels_c64_vl4mm(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilels.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilels_c64_vl4(uint64_t op1, uint64_t op2)
+{
+ return svwhilels_c64(op1, op2, 4);
+}
+
+
+// WHILELT
+
+// CHECK-LABEL: @test_svwhilelt_c8_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilelt_c8_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelt_c8_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilelt_c8(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilelt_c8_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilelt_c8_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelt_c8_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilelt_c8(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilelt_c16_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelt_c16_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelt_c16_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilelt_c16(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilelt_c16_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelt_c16_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c16(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelt_c16_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilelt_c16(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilelt_c32_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelt_c32_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelt_c32_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilelt_c32(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilelt_c32_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelt_c32_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c32(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelt_c32_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilelt_c32(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_svwhilelt_c64_vl2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelt_c64_vl2ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelt_c64_vl2(int64_t op1, int64_t op2)
+{
+ return svwhilelt_c64(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilelt_c64_vl4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z22test_svwhilelt_c64_vl4ll(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.whilelt.c64(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilelt_c64_vl4(int64_t op1, int64_t op2)
+{
+ return svwhilelt_c64(op1, op2, 4);
+}
Index: clang/include/clang/Basic/arm_sve.td
===================================================================
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -2126,6 +2126,14 @@
def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pmi", "Pi", MergeNone, "", [], [ImmCheck<3, ImmCheck0_3>]>;
def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pmi", "Pl", MergeNone, "", [], [ImmCheck<3, ImmCheck0_1>]>;
+def SVWHILEGE_COUNT : SInst<"svwhilege_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilege_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILEGT_COUNT : SInst<"svwhilegt_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilegt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILELE_COUNT : SInst<"svwhilele_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilele_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILELT_COUNT : SInst<"svwhilelt_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilelt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILELO_COUNT : SInst<"svwhilelo_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilelo_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILELS_COUNT : SInst<"svwhilels_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilels_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILEHI_COUNT : SInst<"svwhilehi_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilehi_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILEHS_COUNT : SInst<"svwhilehs_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilehs_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
}
let TargetGuard = "sve2p1" in {
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