Author: Jim Lin Date: 2023-05-22T10:28:27+08:00 New Revision: 33d3d51d77a7fb7ca6b919f9ba47999cd8531844
URL: https://github.com/llvm/llvm-project/commit/33d3d51d77a7fb7ca6b919f9ba47999cd8531844 DIFF: https://github.com/llvm/llvm-project/commit/33d3d51d77a7fb7ca6b919f9ba47999cd8531844.diff LOG: [RISCV] Add missing test for ctz_32 on RV64 Apparently, both of clz and ctz should have tests for _32 version on RV64. Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D150945 Added: Modified: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c Removed: ################################################################################ diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c index e136151e511b3..0133cb1ec202d 100644 --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c @@ -50,6 +50,18 @@ long clz_64(long a) { return __builtin_riscv_clz_64(a); } +// RV64ZBB-LABEL: @ctz_32( +// RV64ZBB-NEXT: entry: +// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV64ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 +// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false) +// RV64ZBB-NEXT: ret i32 [[TMP1]] +// +int ctz_32(int a) { + return __builtin_riscv_ctz_32(a); +} + // RV64ZBB-LABEL: @ctz_64( // RV64ZBB-NEXT: entry: // RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
