CarolineConcatto created this revision.
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Patch by : David Sherwood <david.sherw...@arm.com>
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D150961
Files:
clang/include/clang/Basic/arm_sve.td
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_cntp.c
clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
Index: clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
===================================================================
--- /dev/null
+++ clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 -triple aarch14-none-linux-gnu -target-feature +sve2p1 -fsyntax-only -verify %s
+
+// REQUIRES: aarch14-registered-target
+
+#include <arm_sve.h>
+
+void test_cntp(svcount_t c) {
+ svcntp_c8(c, 1); // expected-error {{argument value 1 is outside the valid range [2, 4]}}
+ svcntp_c11(c, 1); // expected-error {{argument value 1 is outside the valid range [2, 4]}}
+ svcntp_c32(c, 1); // expected-error {{argument value 1 is outside the valid range [2, 4]}}
+ svcntp_c14(c, 1); // expected-error {{argument value 1 is outside the valid range [2, 4]}}
+
+ svcntp_c8(c, 3); // expected-error {{argument should be a multiple of 2}}
+ svcntp_c11(c, 3); // expected-error {{argument should be a multiple of 2}}
+ svcntp_c32(c, 3); // expected-error {{argument should be a multiple of 2}}
+ svcntp_c14(c, 3); // expected-error {{argument should be a multiple of 2}}
+}
+
Index: clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_cntp.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_cntp.c
@@ -0,0 +1,119 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+#include <arm_sve.h>
+
+// CHECK-LABEL: @test_svcntp_c8_vlx2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svcntp_c8_vlx2u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c8_vlx2(svcount_t pnn) {
+ return svcntp_c8(pnn, 2);
+}
+
+// CHECK-LABEL: @test_svcntp_c8_vlx4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svcntp_c8_vlx4u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c8_vlx4(svcount_t pnn) {
+ return svcntp_c8(pnn, 4);
+}
+
+// CHECK-LABEL: @test_svcntp_c16_vlx2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c16_vlx2u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c16_vlx2(svcount_t pnn) {
+ return svcntp_c16(pnn, 2);
+}
+
+// CHECK-LABEL: @test_svcntp_c16_vlx4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c16_vlx4u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c16_vlx4(svcount_t pnn) {
+ return svcntp_c16(pnn, 4);
+}
+
+// CHECK-LABEL: @test_svcntp_c32_vlx2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c32_vlx2u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c32_vlx2(svcount_t pnn) {
+ return svcntp_c32(pnn, 2);
+}
+
+// CHECK-LABEL: @test_svcntp_c32_vlx4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c32_vlx4u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c32_vlx4(svcount_t pnn) {
+ return svcntp_c32(pnn, 4);
+}
+
+// CHECK-LABEL: @test_svcntp_c64_vlx2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c64_vlx2u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c64_vlx2(svcount_t pnn) {
+ return svcntp_c64(pnn, 2);
+}
+
+// CHECK-LABEL: @test_svcntp_c64_vlx4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c64_vlx4u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c64_vlx4(svcount_t pnn) {
+ return svcntp_c64(pnn, 4);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===================================================================
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -2981,6 +2981,11 @@
if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 3))
HasError = true;
break;
+ case SVETypeFlags::ImmCheck2_4_Mul2:
+ if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 2, 4) ||
+ SemaBuiltinConstantArgMultiple(TheCall, ArgNum, 2))
+ HasError = true;
+ break;
}
}
Index: clang/include/clang/Basic/arm_sve.td
===================================================================
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -232,6 +232,7 @@
def ImmCheck0_1 : ImmCheckType<13>; // 0..1
def ImmCheck0_2 : ImmCheckType<14>; // 0..2
def ImmCheck0_3 : ImmCheckType<15>; // 0..3
+def ImmCheck2_4_Mul2 : ImmCheckType<24>; // 2, 4
class ImmCheck<int arg, ImmCheckType kind, int eltSizeArg = -1> {
int Arg = arg;
@@ -2112,6 +2113,7 @@
let TargetGuard = "sve2p1" in {
def SVFCLAMP : SInst<"svclamp[_{d}]", "dddd", "hfd", MergeNone, "aarch64_sve_fclamp", [], []>;
def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone, "aarch64_sve_ptrue_{d}", [IsOverloadNone], []>;
+ def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, "aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
}
let TargetGuard = "sve2p1" in {
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