eopXD added inline comments.
================ Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c:1 -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // REQUIRES: riscv-registered-target ---------------- kito-cheng wrote: > ` UTC_ARGS: --version 2`? Cleared the diff with an NFC commit. ================ Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:1418 + def int_riscv_vreinterpret_v + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], ---------------- craig.topper wrote: > craig.topper wrote: > > Do we need an intrinsic? > > > > m1 -> mask is bitcast m1 vscale type to <vscale x 64 x i1> and a > > llvm.experimental.vector.extract > > mask -> m1 is llvm.experimental.vector.insert to <vscale x 64 x i1> and a > > bitcast. > oops there's no experimental in the insert/extract names. Replacing with insert/extract here with `index = 0`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149642/new/ https://reviews.llvm.org/D149642 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
