This revision was not accepted when it landed; it landed in state "Needs Review". This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf0415f2a456d: Re-land "[AMDGPU] Define data layout entries for buffers"" (authored by krzysz00).
Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149776/new/ https://reviews.llvm.org/D149776 Files: clang/lib/Basic/Targets/AMDGPU.cpp clang/test/CodeGen/target-data.c clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl llvm/docs/AMDGPUUsage.rst llvm/lib/IR/AutoUpgrade.cpp llvm/lib/Target/AMDGPU/AMDGPU.h llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll llvm/test/CodeGen/AMDGPU/addrspacecast-captured.ll llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll llvm/test/CodeGen/AMDGPU/loop-idiom.ll llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll llvm/test/CodeGen/AMDGPU/nullptr.ll llvm/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll llvm/test/CodeGen/AMDGPU/unroll.ll llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll llvm/test/Instrumentation/AddressSanitizer/AMDGPU/adaptive_constant_global_redzones.ll llvm/test/Instrumentation/AddressSanitizer/AMDGPU/adaptive_global_redzones.ll llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_lds.ll llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_scratch.ll llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll llvm/test/Instrumentation/AddressSanitizer/AMDGPU/global_metadata_addrspacecasts.ll llvm/test/Instrumentation/AddressSanitizer/AMDGPU/no_redzones_in_lds_globals.ll llvm/test/Instrumentation/AddressSanitizer/AMDGPU/no_redzones_in_scratch_globals.ll llvm/test/Transforms/AlignmentFromAssumptions/amdgpu-crash.ll llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll llvm/test/Transforms/EarlyCSE/AMDGPU/memrealtime.ll llvm/test/Transforms/IndVarSimplify/AMDGPU/no-widen-to-i64.ll llvm/test/Transforms/InferAddressSpaces/AMDGPU/noop-ptrint-pair.ll llvm/test/Transforms/InferAddressSpaces/AMDGPU/ptrmask.ll llvm/test/Transforms/InferAddressSpaces/X86/noop-ptrint-pair.ll llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-alloca-argument.ll llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll llvm/test/Transforms/InstCombine/alloca-in-non-alloca-as.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/aa-metadata.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/gep-bitcast.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/insertion-point.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/interleaved-mayalias-store.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/invariant-load.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/no-implicit-float.ll llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/optnone.ll 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llvm/test/Transforms/SLPVectorizer/AMDGPU/address-space-ptr-sze-gep-index-assert.ll llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
