craig.topper added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:169 +def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, + [Feature64Bit, ---------------- I would prefer that we add sifive-x280 in a single patch with all of its features. Currently zba/zbb are in a different patch. I don't think there's any restriction about adding a feature to a CPU without it being present in the scheduler model. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149495/new/ https://reviews.llvm.org/D149495 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
