sstwcw created this revision.
Herald added projects: All, clang, clang-format.
Herald added a subscriber: cfe-commits.
Herald added reviewers: rymiel, HazardyKnusperkeks, owenpan, MyDeveloperDay.
sstwcw requested review of this revision.
Before:
module x
#( //
parameter x)
( //
input y);
endmodule
After:
module x
#(//
parameter x)
(//
input y);
endmodule
If the first line in a port or parameter list is not a comment, the
following lines would be aligned to the first line as intended:
module x
#(parameter x1,
parameter x2)
(input y,
input y2);
endmodule
Previously, the indentation would be changed to an extra continuation
indentation relative to the start of the parenthesis or the hash if
the first token inside the parentheses is a comment. It is a feature
introduced in ddaa9be97839. The feature enabled one to insert a `//`
comment right after an opening parentheses to put the function
arguments on a new line with a small indentation regardless of how
long the function name is, like this:
someFunction(anotherFunction( // Force break.
parameter));
`
People are unlikely to use this feature in a Verilog port list because
the formatter already puts the port list on its own lines. A comment
at the start of a port list is probably a comment for the port on the
next line.
We also removed the space before the comment so that its indentation
would be same as that for a line comment anywhere else in the port
list.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D149562
Files:
clang/docs/ClangFormatStyleOptions.rst
clang/include/clang/Format/Format.h
clang/lib/Format/ContinuationIndenter.cpp
clang/lib/Format/FormatToken.h
clang/lib/Format/TokenAnnotator.cpp
clang/lib/Format/UnwrappedLineParser.cpp
clang/unittests/Format/FormatTestVerilog.cpp
Index: clang/unittests/Format/FormatTestVerilog.cpp
===================================================================
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -484,6 +484,15 @@
" (input var x `a, //\n"
" b);\n"
"endmodule");
+ // A line comment shouldn't disrupt the indentation of the port list.
+ verifyFormat("extern module x\n"
+ " (//\n"
+ " output y);");
+ verifyFormat("extern module x\n"
+ " #(//\n"
+ " parameter x)\n"
+ " (//\n"
+ " output y);");
// With a concatenation in the names.
auto Style = getDefaultStyle();
Style.ColumnLimit = 40;
Index: clang/lib/Format/UnwrappedLineParser.cpp
===================================================================
--- clang/lib/Format/UnwrappedLineParser.cpp
+++ clang/lib/Format/UnwrappedLineParser.cpp
@@ -4194,11 +4194,14 @@
if (FormatTok->is(Keywords.kw_verilogHash)) {
NewLine();
nextToken();
- if (FormatTok->is(tok::l_paren))
+ if (FormatTok->is(tok::l_paren)) {
+ FormatTok->setFinalizedType(TT_VerilogMultiLineListLParen);
parseParens();
+ }
}
if (FormatTok->is(tok::l_paren)) {
NewLine();
+ FormatTok->setFinalizedType(TT_VerilogMultiLineListLParen);
parseParens();
}
Index: clang/lib/Format/TokenAnnotator.cpp
===================================================================
--- clang/lib/Format/TokenAnnotator.cpp
+++ clang/lib/Format/TokenAnnotator.cpp
@@ -3312,6 +3312,8 @@
if (Prev->is(BK_BracedInit) && Prev->opensScope()) {
Current->SpacesRequiredBefore =
(Style.Cpp11BracedListStyle && !Style.SpacesInParentheses) ? 0 : 1;
+ } else if (Prev->is(TT_VerilogMultiLineListLParen)) {
+ Current->SpacesRequiredBefore = 0;
} else {
Current->SpacesRequiredBefore = Style.SpacesBeforeTrailingComments;
}
Index: clang/lib/Format/FormatToken.h
===================================================================
--- clang/lib/Format/FormatToken.h
+++ clang/lib/Format/FormatToken.h
@@ -156,6 +156,9 @@
/* list of port connections or parameters in a module instantiation */ \
TYPE(VerilogInstancePortComma) \
TYPE(VerilogInstancePortLParen) \
+ /* A parenthesized list within which line breaks are inserted by the \
+ * formatter, for example the list of ports in a module header. */ \
+ TYPE(VerilogMultiLineListLParen) \
/* for the base in a number literal, not including the quote */ \
TYPE(VerilogNumberBase) \
/* like `(strong1, pull0)` */ \
Index: clang/lib/Format/ContinuationIndenter.cpp
===================================================================
--- clang/lib/Format/ContinuationIndenter.cpp
+++ clang/lib/Format/ContinuationIndenter.cpp
@@ -748,7 +748,8 @@
!CurrentState.IsCSharpGenericTypeConstraint && Previous.opensScope() &&
Previous.isNot(TT_ObjCMethodExpr) && Previous.isNot(TT_RequiresClause) &&
!(Current.MacroParent && Previous.MacroParent) &&
- (Current.isNot(TT_LineComment) || Previous.is(BK_BracedInit))) {
+ (Current.isNot(TT_LineComment) ||
+ Previous.isOneOf(BK_BracedInit, TT_VerilogMultiLineListLParen))) {
CurrentState.Indent = State.Column + Spaces;
CurrentState.IsAligned = true;
}
Index: clang/include/clang/Format/Format.h
===================================================================
--- clang/include/clang/Format/Format.h
+++ clang/include/clang/Format/Format.h
@@ -4019,9 +4019,12 @@
/// The number of spaces before trailing line comments
/// (``//`` - comments).
///
- /// This does not affect trailing block comments (``/*`` - comments) as
- /// those commonly have different usage patterns and a number of special
- /// cases.
+ /// This does not affect trailing block comments (``/*`` - comments) as those
+ /// commonly have different usage patterns and a number of special cases. In
+ /// the case of Verilog, it doesn't affect a comment right after the opening
+ /// parenthesis in the port or parameter list in a module header, because it
+ /// is probably for the port on the following line instead of the parenthesis
+ /// it follows.
/// \code
/// SpacesBeforeTrailingComments: 3
/// void f() {
Index: clang/docs/ClangFormatStyleOptions.rst
===================================================================
--- clang/docs/ClangFormatStyleOptions.rst
+++ clang/docs/ClangFormatStyleOptions.rst
@@ -5069,9 +5069,12 @@
The number of spaces before trailing line comments
(``//`` - comments).
- This does not affect trailing block comments (``/*`` - comments) as
- those commonly have different usage patterns and a number of special
- cases.
+ This does not affect trailing block comments (``/*`` - comments) as those
+ commonly have different usage patterns and a number of special cases. In
+ the case of Verilog, it doesn't affect a comment right after the opening
+ parenthesis in the port or parameter list in a module header, because it
+ is probably for the port on the following line instead of the parenthesis
+ it follows.
.. code-block:: c++
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