[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

[John McCall via Phabricator via cfe-commits]

rjmccall added a comment.

Thanks, a couple very minor fixes / requests, but feel free to commit 
afterwards.



================
Comment at: clang/include/clang/Basic/AttrDocs.td:2323
+  let Content = [{
+The ``riscv_rvv_vector_bits(N)`` attribute is used to define fixed-length
+variants of sizeless types.
----------------
Maybe this is obvious from the attribute name, but it's better to be clear.


================
Comment at: clang/include/clang/Basic/AttrDocs.td:2332
+
+  #if define(__riscv_v_fixed_vlen)
+  typedef vint8m1_t fixed_vint8m1_t 
__attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
----------------



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145088/new/

https://reviews.llvm.org/D145088

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