aeubanks added inline comments.

================
Comment at: llvm/test/Transforms/PhaseOrdering/X86/pr52289.ll:9
 ; CHECK-NEXT:  if.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[A:%.*]], 1
+; CHECK-NEXT:    [[CONV:%.*]] = and i32 [[TMP0]], 8
----------------
aeubanks wrote:
> this is an instcombine issue related to 
> https://github.com/llvm/llvm-project/issues/51631 which has some bugs split 
> out from it that are still open
https://github.com/llvm/llvm-project/issues/51744 and 
https://github.com/llvm/llvm-project/issues/51748 are the open issues for this. 
is it ok to regress this for now given that the original motivation for this 
was found via fuzzing and not real world code?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145265/new/

https://reviews.llvm.org/D145265

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