craig.topper created this revision.
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the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217,
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To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.
D146449 <https://reviews.llvm.org/D146449> already updated comments. Strings
may have more user impact.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D146451
Files:
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Driver/Options.td
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/O0-pipeline.ll
llvm/test/CodeGen/RISCV/O3-pipeline.ll
llvm/utils/TableGen/TableGen.cpp
Index: llvm/utils/TableGen/TableGen.cpp
===================================================================
--- llvm/utils/TableGen/TableGen.cpp
+++ llvm/utils/TableGen/TableGen.cpp
@@ -101,7 +101,7 @@
clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
"Generate pseudo instruction lowering"),
clEnumValN(GenCompressInst, "gen-compress-inst-emitter",
- "Generate RISCV compressed instructions."),
+ "Generate compressed instructions."),
clEnumValN(GenAsmMatcher, "gen-asm-matcher",
"Generate assembly instruction matcher"),
clEnumValN(GenDAGISel, "gen-dag-isel",
@@ -148,7 +148,7 @@
clEnumValN(GenDXILOperation, "gen-dxil-operation",
"Generate DXIL operation information"),
clEnumValN(GenRISCVTargetDef, "gen-riscv-target-def",
- "Generate the list of CPU for RISCV")));
+ "Generate the list of CPU for RISC-V")));
cl::OptionCategory PrintEnumsCat("Options for -print-enums");
cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
cl::value_desc("class name"),
Index: llvm/test/CodeGen/RISCV/O3-pipeline.ll
===================================================================
--- llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -28,8 +28,8 @@
; CHECK-NEXT: Expand Atomic instructions
; CHECK-NEXT: Dominator Tree Construction
; CHECK-NEXT: Natural Loop Information
-; CHECK-NEXT: RISCV gather/scatter lowering
-; CHECK-NEXT: RISCV CodeGenPrepare
+; CHECK-NEXT: RISC-V gather/scatter lowering
+; CHECK-NEXT: RISC-V CodeGenPrepare
; CHECK-NEXT: Module Verifier
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Canonicalize natural loops
@@ -79,7 +79,7 @@
; CHECK-NEXT: Assignment Tracking Analysis
; CHECK-NEXT: Lazy Branch Probability Analysis
; CHECK-NEXT: Lazy Block Frequency Analysis
-; CHECK-NEXT: RISCV DAG->DAG Pattern Instruction Selection
+; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Early Tail Duplication
@@ -103,13 +103,13 @@
; CHECK-NEXT: Machine Trace Metrics
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine InstCombiner
-; RV64-NEXT: RISCV sext.w Removal
-; RV64-NEXT: RISCV Strip W Suffix
-; CHECK-NEXT: RISCV Pre-RA pseudo instruction expansion pass
-; CHECK-NEXT: RISCV Merge Base Offset
-; CHECK-NEXT: RISCV Insert VSETVLI pass
+; RV64-NEXT: RISC-V sext.w Removal
+; RV64-NEXT: RISC-V Strip W Suffix
+; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V Merge Base Offset
+; CHECK-NEXT: RISC-V Insert VSETVLI pass
; CHECK-NEXT: Detect Dead Lanes
-; CHECK-NEXT: RISCV init undef pass
+; CHECK-NEXT: RISC-V init undef pass
; CHECK-NEXT: Process Implicit Definitions
; CHECK-NEXT: Remove unreachable machine basic blocks
; CHECK-NEXT: Live Variable Analysis
@@ -136,7 +136,7 @@
; CHECK-NEXT: Stack Slot Coloring
; CHECK-NEXT: Machine Copy Propagation Pass
; CHECK-NEXT: Machine Loop Invariant Code Motion
-; CHECK-NEXT: RISCV Redundant Copy Elimination
+; CHECK-NEXT: RISC-V Redundant Copy Elimination
; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
; CHECK-NEXT: Fixup Statepoint Caller Saved
; CHECK-NEXT: PostRA Machine Sink
@@ -165,7 +165,7 @@
; CHECK-NEXT: Insert XRay ops
; CHECK-NEXT: Implement the 'patchable-function' attribute
; CHECK-NEXT: Branch relaxation pass
-; CHECK-NEXT: RISCV Make Compressible
+; CHECK-NEXT: RISC-V Make Compressible
; CHECK-NEXT: Machine Copy Propagation Pass
; CHECK-NEXT: Contiguously Lay Out Funclets
; CHECK-NEXT: StackMap Liveness Analysis
@@ -176,9 +176,9 @@
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Stack Frame Layout Analysis
-; CHECK-NEXT: RISCV pseudo instruction expansion pass
-; CHECK-NEXT: RISCV atomic pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
-; CHECK-NEXT: RISCV Assembly Printer
+; CHECK-NEXT: RISC-V Assembly Printer
; CHECK-NEXT: Free MachineFunction
Index: llvm/test/CodeGen/RISCV/O0-pipeline.ll
===================================================================
--- llvm/test/CodeGen/RISCV/O0-pipeline.ll
+++ llvm/test/CodeGen/RISCV/O0-pipeline.ll
@@ -36,11 +36,11 @@
; CHECK-NEXT: Insert stack protectors
; CHECK-NEXT: Module Verifier
; CHECK-NEXT: Assignment Tracking Analysis
-; CHECK-NEXT: RISCV DAG->DAG Pattern Instruction Selection
+; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Local Stack Slot Allocation
-; CHECK-NEXT: RISCV Pre-RA pseudo instruction expansion pass
-; CHECK-NEXT: RISCV Insert VSETVLI pass
+; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V Insert VSETVLI pass
; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Fast Register Allocator
@@ -55,7 +55,7 @@
; CHECK-NEXT: Insert XRay ops
; CHECK-NEXT: Implement the 'patchable-function' attribute
; CHECK-NEXT: Branch relaxation pass
-; CHECK-NEXT: RISCV Make Compressible
+; CHECK-NEXT: RISC-V Make Compressible
; CHECK-NEXT: Contiguously Lay Out Funclets
; CHECK-NEXT: StackMap Liveness Analysis
; CHECK-NEXT: Live DEBUG_VALUE analysis
@@ -63,9 +63,9 @@
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Stack Frame Layout Analysis
-; CHECK-NEXT: RISCV pseudo instruction expansion pass
-; CHECK-NEXT: RISCV atomic pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
-; CHECK-NEXT: RISCV Assembly Printer
+; CHECK-NEXT: RISC-V Assembly Printer
; CHECK-NEXT: Free MachineFunction
Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -68,7 +68,7 @@
static cl::opt<bool> EnableRISCVCopyPropagation(
"riscv-enable-copy-propagation",
- cl::desc("Enable the copy propagation with RISCV copy instr"),
+ cl::desc("Enable the copy propagation with RISC-V copy instr"),
cl::init(true), cl::Hidden);
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
Index: llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp
+++ llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp
@@ -40,14 +40,14 @@
MachineFunctionPass::getAnalysisUsage(AU);
}
- StringRef getPassName() const override { return "RISCV Strip W Suffix"; }
+ StringRef getPassName() const override { return "RISC-V Strip W Suffix"; }
};
} // end anonymous namespace
char RISCVStripWSuffix::ID = 0;
INITIALIZE_PASS(RISCVStripWSuffix, "riscv-strip-w-suffix",
- "RISCV Strip W Suffix", false, false)
+ "RISC-V Strip W Suffix", false, false)
FunctionPass *llvm::createRISCVStripWSuffixPass() {
return new RISCVStripWSuffix();
Index: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -47,13 +47,13 @@
MachineFunctionPass::getAnalysisUsage(AU);
}
- StringRef getPassName() const override { return "RISCV sext.w Removal"; }
+ StringRef getPassName() const override { return "RISC-V sext.w Removal"; }
};
} // end anonymous namespace
char RISCVSExtWRemoval::ID = 0;
-INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISCV sext.w Removal", false,
+INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISC-V sext.w Removal", false,
false)
FunctionPass *llvm::createRISCVSExtWRemovalPass() {
Index: llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
+++ llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
@@ -56,7 +56,7 @@
}
StringRef getPassName() const override {
- return "RISCV Redundant Copy Elimination";
+ return "RISC-V Redundant Copy Elimination";
}
private:
@@ -68,7 +68,7 @@
char RISCVRedundantCopyElimination::ID = 0;
INITIALIZE_PASS(RISCVRedundantCopyElimination, "riscv-copyelim",
- "RISCV redundant copy elimination pass", false, false)
+ "RISC-V Redundant Copy Elimination", false, false)
static bool
guaranteesZeroRegInBlock(MachineBasicBlock &MBB,
Index: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
+++ llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
@@ -39,7 +39,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-init-undef"
-#define RISCV_INIT_UNDEF_NAME "RISCV init undef pass"
+#define RISCV_INIT_UNDEF_NAME "RISC-V init undef pass"
namespace {
Index: llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+++ llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
@@ -23,7 +23,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-merge-base-offset"
-#define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset"
+#define RISCV_MERGE_BASE_OFFSET_NAME "RISC-V Merge Base Offset"
namespace {
struct RISCVMergeBaseOffsetOpt : public MachineFunctionPass {
Index: llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -75,7 +75,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-make-compressible"
-#define RISCV_COMPRESS_INSTRS_NAME "RISCV Make Compressible"
+#define RISCV_COMPRESS_INSTRS_NAME "RISC-V Make Compressible"
namespace {
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -951,7 +951,7 @@
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 3 || Cond.size() == 0) &&
- "RISCV branch conditions have two components!");
+ "RISC-V branch conditions have two components!");
// Unconditional branch.
if (Cond.empty()) {
Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -32,7 +32,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-insert-vsetvli"
-#define RISCV_INSERT_VSETVLI_NAME "RISCV Insert VSETVLI pass"
+#define RISCV_INSERT_VSETVLI_NAME "RISC-V Insert VSETVLI pass"
static cl::opt<bool> DisableInsertVSETVLPHIOpt(
"riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden,
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -26,7 +26,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-isel"
-#define PASS_NAME "RISCV DAG->DAG Pattern Instruction Selection"
+#define PASS_NAME "RISC-V DAG->DAG Pattern Instruction Selection"
namespace llvm::RISCV {
#define GET_RISCVVSSEGTable_IMPL
@@ -134,7 +134,7 @@
}
if (Result) {
- LLVM_DEBUG(dbgs() << "RISCV DAG preprocessing replacing:\nOld: ");
+ LLVM_DEBUG(dbgs() << "RISC-V DAG preprocessing replacing:\nOld: ");
LLVM_DEBUG(N->dump(CurDAG));
LLVM_DEBUG(dbgs() << "\nNew: ");
LLVM_DEBUG(Result->dump(CurDAG));
Index: llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
@@ -59,7 +59,7 @@
}
StringRef getPassName() const override {
- return "RISCV gather/scatter lowering";
+ return "RISC-V gather/scatter lowering";
}
private:
@@ -81,7 +81,7 @@
char RISCVGatherScatterLowering::ID = 0;
INITIALIZE_PASS(RISCVGatherScatterLowering, DEBUG_TYPE,
- "RISCV gather/scatter lowering pass", false, false)
+ "RISC-V gather/scatter lowering pass", false, false)
FunctionPass *llvm::createRISCVGatherScatterLoweringPass() {
return new RISCVGatherScatterLowering();
Index: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -23,8 +23,8 @@
using namespace llvm;
-#define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass"
-#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISCV Pre-RA pseudo instruction expansion pass"
+#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
+#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
namespace {
Index: llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+++ llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
@@ -24,7 +24,7 @@
using namespace llvm;
#define RISCV_EXPAND_ATOMIC_PSEUDO_NAME \
- "RISCV atomic pseudo instruction expansion pass"
+ "RISC-V atomic pseudo instruction expansion pass"
namespace {
Index: llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+++ llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
@@ -26,7 +26,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-codegenprepare"
-#define PASS_NAME "RISCV CodeGenPrepare"
+#define PASS_NAME "RISC-V CodeGenPrepare"
STATISTIC(NumZExtToSExt, "Number of SExt instructions converted to ZExt");
Index: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -53,7 +53,7 @@
std::unique_ptr<MCStreamer> Streamer)
: AsmPrinter(TM, std::move(Streamer)) {}
- StringRef getPassName() const override { return "RISCV Assembly Printer"; }
+ StringRef getPassName() const override { return "RISC-V Assembly Printer"; }
bool runOnMachineFunction(MachineFunction &MF) override;
Index: clang/include/clang/Driver/Options.td
===================================================================
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -185,7 +185,7 @@
def m_x86_Features_Group : OptionGroup<"<x86 features group>">,
Group<m_Group>, Flags<[CoreOption]>, DocName<"X86">;
def m_riscv_Features_Group : OptionGroup<"<riscv features group>">,
- Group<m_Group>, DocName<"RISCV">;
+ Group<m_Group>, DocName<"RISC-V">;
def m_libc_Group : OptionGroup<"<m libc group>">, Group<m_mips_Features_Group>,
Flags<[HelpHidden]>;
Index: clang/include/clang/Basic/AttrDocs.td
===================================================================
--- clang/include/clang/Basic/AttrDocs.td
+++ clang/include/clang/Basic/AttrDocs.td
@@ -2293,7 +2293,7 @@
def RISCVInterruptDocs : Documentation {
let Category = DocCatFunction;
- let Heading = "interrupt (RISCV)";
+ let Heading = "interrupt (RISC-V)";
let Content = [{
Clang supports the GNU style ``__attribute__((interrupt))`` attribute on RISCV
targets. This attribute may be attached to a function definition and instructs
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