craig.topper updated this revision to Diff 506670. craig.topper added a comment. Herald added subscribers: Sanitizers, Enna1, emaste. Herald added a reviewer: MaskRay. Herald added a project: Sanitizers.
More files Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146449/new/ https://reviews.llvm.org/D146449 Files: clang/lib/Basic/Targets/RISCV.cpp clang/lib/Basic/Targets/RISCV.h clang/lib/CodeGen/TargetInfo.cpp clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/lib/Driver/ToolChains/Arch/RISCV.h clang/lib/Driver/ToolChains/RISCVToolchain.cpp clang/lib/Driver/ToolChains/RISCVToolchain.h compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h lld/ELF/InputSection.cpp llvm/include/llvm/Support/RISCVISAInfo.h llvm/include/llvm/TargetParser/RISCVTargetParser.h llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h llvm/lib/Target/RISCV/RISCV.h llvm/lib/Target/RISCV/RISCV.td llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp llvm/lib/Target/RISCV/RISCVCallingConv.td llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVFrameLowering.cpp llvm/lib/Target/RISCV/RISCVFrameLowering.h llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.h llvm/lib/Target/RISCV/RISCVInstrFormats.td llvm/lib/Target/RISCV/RISCVInstrFormatsC.td llvm/lib/Target/RISCV/RISCVInstrFormatsV.td llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.h llvm/lib/Target/RISCV/RISCVInstrInfo.td llvm/lib/Target/RISCV/RISCVInstrInfoC.td llvm/lib/Target/RISCV/RISCVMCInstLower.cpp llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h llvm/lib/Target/RISCV/RISCVMacroFusion.cpp llvm/lib/Target/RISCV/RISCVMacroFusion.h llvm/lib/Target/RISCV/RISCVProcessors.td llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp llvm/lib/Target/RISCV/RISCVRegisterInfo.h llvm/lib/Target/RISCV/RISCVSchedule.td llvm/lib/Target/RISCV/RISCVScheduleV.td llvm/lib/Target/RISCV/RISCVScheduleZb.td llvm/lib/Target/RISCV/RISCVSubtarget.cpp llvm/lib/Target/RISCV/RISCVSubtarget.h llvm/lib/Target/RISCV/RISCVTargetMachine.cpp llvm/lib/Target/RISCV/RISCVTargetMachine.h llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp llvm/lib/Target/RISCV/RISCVTargetObjectFile.h llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h llvm/lib/TargetParser/RISCVTargetParser.cpp llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
Index: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp =================================================================== --- llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -1,4 +1,4 @@ -//===- RISCVTargetDefEmitter.cpp - Generate lists of RISCV CPUs -----------===// +//===- RISCVTargetDefEmitter.cpp - Generate lists of RISC-V CPUs ----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -20,7 +20,7 @@ using ISAInfoTy = llvm::Expected<std::unique_ptr<RISCVISAInfo>>; // We can generate march string from target features as what has been described -// in RISCV ISA specification (version 20191213) 'Chapter 27. ISA Extension +// in RISC-V ISA specification (version 20191213) 'Chapter 27. ISA Extension // Naming Conventions'. // // This is almost the same as RISCVFeatures::parseFeatureBits, except that we Index: llvm/lib/TargetParser/RISCVTargetParser.cpp =================================================================== --- llvm/lib/TargetParser/RISCVTargetParser.cpp +++ llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // // This file implements a target parser to recognise hardware features -// FOR RISC-V CPUS. +// for RISC-V CPUs. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h =================================================================== --- llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h +++ llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h @@ -1,4 +1,4 @@ -//===-- RISCVTargetInfo.h - RISCV Target Implementation ---------*- C++ -*-===// +//===-- RISCVTargetInfo.h - RISC-V Target Implementation --------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp +++ llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp @@ -1,4 +1,4 @@ -//===-- RISCVTargetInfo.cpp - RISCV Target Implementation -----------------===// +//===-- RISCVTargetInfo.cpp - RISC-V Target Implementation ----------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -1567,7 +1567,7 @@ bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) { - // RISCV specific here are "instruction number 1st priority". + // RISC-V specific here are "instruction number 1st priority". return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) < Index: llvm/lib/Target/RISCV/RISCVTargetObjectFile.h =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetObjectFile.h +++ llvm/lib/Target/RISCV/RISCVTargetObjectFile.h @@ -1,4 +1,4 @@ -//===-- RISCVTargetObjectFile.h - RISCV Object Info -*- C++ ---------*-===// +//===-- RISCVTargetObjectFile.h - RISC-V Object Info ------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -13,7 +13,7 @@ namespace llvm { -/// This implementation is used for RISCV ELF targets. +/// This implementation is used for RISC-V ELF targets. class RISCVELFTargetObjectFile : public TargetLoweringObjectFileELF { MCSection *SmallDataSection; MCSection *SmallBSSSection; Index: llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp +++ llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp @@ -1,4 +1,4 @@ -//===-- RISCVTargetObjectFile.cpp - RISCV Object Info -----------------===// +//===-- RISCVTargetObjectFile.cpp - RISC-V Object Info --------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVTargetMachine.h =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetMachine.h +++ llvm/lib/Target/RISCV/RISCVTargetMachine.h @@ -1,4 +1,4 @@ -//===-- RISCVTargetMachine.h - Define TargetMachine for RISCV ---*- C++ -*-===// +//===-- RISCVTargetMachine.h - Define TargetMachine for RISC-V --*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file declares the RISCV specific subclass of TargetMachine. +// This file declares the RISC-V specific subclass of TargetMachine. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -1,4 +1,4 @@ -//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===// +//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISC-V ----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// Implements the info about RISCV target spec. +// Implements the info about RISC-V target spec. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVSubtarget.h =================================================================== --- llvm/lib/Target/RISCV/RISCVSubtarget.h +++ llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -1,4 +1,4 @@ -//===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===// +//===-- RISCVSubtarget.h - Define Subtarget for the RISC-V ------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file declares the RISCV specific subclass of TargetSubtargetInfo. +// This file declares the RISC-V specific subclass of TargetSubtargetInfo. // //===----------------------------------------------------------------------===// @@ -101,7 +101,7 @@ Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; } Align getPrefLoopAlignment() const { return PrefLoopAlignment; } - /// Returns RISCV processor family. + /// Returns RISC-V processor family. /// Avoid this function! CPU specifics should be kept local to this class /// and preferably modeled with SubtargetFeatures or properties in /// initializeProperties(). Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVSubtarget.cpp +++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp @@ -1,4 +1,4 @@ -//===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===// +//===-- RISCVSubtarget.cpp - RISC-V Subtarget Information -----------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file implements the RISCV specific subclass of TargetSubtargetInfo. +// This file implements the RISC-V specific subclass of TargetSubtargetInfo. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVScheduleZb.td =================================================================== --- llvm/lib/Target/RISCV/RISCVScheduleZb.td +++ llvm/lib/Target/RISCV/RISCVScheduleZb.td @@ -1,4 +1,4 @@ -//===-- RISCVScheduleB.td - RISCV Scheduling Definitions B -*- tablegen -*-===// +//===- RISCVScheduleB.td - RISC-V Scheduling Definitions B -*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVScheduleV.td =================================================================== --- llvm/lib/Target/RISCV/RISCVScheduleV.td +++ llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -1,4 +1,4 @@ -//===-- RISCVScheduleV.td - RISCV Scheduling Definitions V -*- tablegen -*-===// +//===- RISCVScheduleV.td - RISC-V Scheduling Definitions V -*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVSchedule.td =================================================================== --- llvm/lib/Target/RISCV/RISCVSchedule.td +++ llvm/lib/Target/RISCV/RISCVSchedule.td @@ -1,4 +1,4 @@ -//===-- RISCVSchedule.td - RISCV Scheduling Definitions ----*- tablegen -*-===// +//===-- RISCVSchedule.td - RISC-V Scheduling Definitions ---*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVRegisterInfo.h +++ llvm/lib/Target/RISCV/RISCVRegisterInfo.h @@ -1,4 +1,4 @@ -//===-- RISCVRegisterInfo.h - RISCV Register Information Impl ---*- C++ -*-===// +//===-- RISCVRegisterInfo.h - RISC-V Register Information Impl --*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the RISCV implementation of the TargetRegisterInfo class. +// This file contains the RISC-V implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -1,4 +1,4 @@ -//===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===// +//===-- RISCVRegisterInfo.cpp - RISC-V Register Information -----*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the RISCV implementation of the TargetRegisterInfo class. +// This file contains the RISC-V implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp +++ llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp @@ -1,4 +1,4 @@ -//=- RISCVRedundantCopyElimination.cpp - Remove useless copy for RISCV ------=// +//=- RISCVRedundantCopyElimination.cpp - Remove useless copy for RISC-V -----=// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVProcessors.td =================================================================== --- llvm/lib/Target/RISCV/RISCVProcessors.td +++ llvm/lib/Target/RISCV/RISCVProcessors.td @@ -1,4 +1,4 @@ -//===-- RISCVProcessors.td - RISCV Processors --------------*- tablegen -*-===// +//===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVMacroFusion.h =================================================================== --- llvm/lib/Target/RISCV/RISCVMacroFusion.h +++ llvm/lib/Target/RISCV/RISCVMacroFusion.h @@ -1,4 +1,4 @@ -//===- RISCVMacroFusion.h - RISCV Macro Fusion ----------------------------===// +//===- RISCVMacroFusion.h - RISC-V Macro Fusion -----------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// // -/// \file This file contains the RISCV definition of the DAG scheduling mutation -/// to pair instructions back to back. +/// \file This file contains the RISC-V definition of the DAG scheduling +/// mutation to pair instructions back to back. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVMacroFusion.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVMacroFusion.cpp +++ llvm/lib/Target/RISCV/RISCVMacroFusion.cpp @@ -1,4 +1,4 @@ -//===- RISCVMacroFusion.cpp - RISCV Macro Fusion --------------------------===// +//===- RISCVMacroFusion.cpp - RISC-V Macro Fusion -------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -/// \file This file contains the RISCV implementation of the DAG scheduling +/// \file This file contains the RISC-V implementation of the DAG scheduling /// mutation to pair instructions back to back. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h +++ llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h @@ -1,4 +1,4 @@ -//=- RISCVMachineFunctionInfo.h - RISCV machine function info -----*- C++ -*-=// +//=- RISCVMachineFunctionInfo.h - RISC-V machine function info ----*- C++ -*-=// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp +++ llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp @@ -1,4 +1,4 @@ -//=- RISCVMachineFunctionInfo.cpp - RISCV machine function info ---*- C++ -*-=// +//=- RISCVMachineFunctionInfo.cpp - RISC-V machine function info --*- C++ -*-=// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVMCInstLower.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVMCInstLower.cpp +++ llvm/lib/Target/RISCV/RISCVMCInstLower.cpp @@ -1,4 +1,4 @@ -//===-- RISCVMCInstLower.cpp - Convert RISCV MachineInstr to an MCInst ------=// +//===-- RISCVMCInstLower.cpp - Convert RISC-V MachineInstr to an MCInst -----=// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains code to lower RISCV MachineInstrs to their corresponding +// This file contains code to lower RISC-V MachineInstrs to their corresponding // MCInst records. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVInstrInfoC.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -1,4 +1,4 @@ -//===- RISCVInstrInfoC.td - Compressed RISCV instructions -*- tblgen-*-----===// +//===- RISCVInstrInfoC.td - Compressed RISC-V instructions -*- tblgen-*----===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1,4 +1,4 @@ -//===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===// +//===-- RISCVInstrInfo.td - Target Description for RISC-V --*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVInstrInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -1,4 +1,4 @@ -//===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===// +//===-- RISCVInstrInfo.h - RISC-V Instruction Information -------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the RISCV implementation of the TargetInstrInfo class. +// This file contains the RISC-V implementation of the TargetInstrInfo class. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1,4 +1,4 @@ -//===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===// +//===-- RISCVInstrInfo.cpp - RISC-V Instruction Information -----*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the RISCV implementation of the TargetInstrInfo class. +// This file contains the RISC-V implementation of the TargetInstrInfo class. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVInstrFormatsV.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrFormatsV.td +++ llvm/lib/Target/RISCV/RISCVInstrFormatsV.td @@ -1,4 +1,4 @@ -//===-- RISCVInstrFormatsV.td - RISCV V Instruction Formats --*- tablegen -*-=// +//===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVInstrFormatsC.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrFormatsC.td +++ llvm/lib/Target/RISCV/RISCVInstrFormatsC.td @@ -1,4 +1,4 @@ -//===-- RISCVInstrFormatsC.td - RISCV C Instruction Formats --*- tablegen -*-=// +//===-- RISCVInstrFormatsC.td - RISC-V C Instruction Formats -*- tablegen -*-=// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVInstrFormats.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -1,4 +1,4 @@ -//===-- RISCVInstrFormats.td - RISCV Instruction Formats ---*- tablegen -*-===// +//===-- RISCVInstrFormats.td - RISC-V Instruction Formats --*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVISelLowering.h =================================================================== --- llvm/lib/Target/RISCV/RISCVISelLowering.h +++ llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -1,4 +1,4 @@ -//===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// +//===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file defines the interfaces that RISCV uses to lower LLVM code into a +// This file defines the interfaces that RISC-V uses to lower LLVM code into a // selection DAG. // //===----------------------------------------------------------------------===// @@ -802,7 +802,7 @@ /// Disable normalizing /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) - /// RISCV doesn't have flags so it's better to perform the and/or in a GPR. + /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR. bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override { return false; }; Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1,4 +1,4 @@ -//===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===// +//===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation -------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file defines the interfaces that RISCV uses to lower LLVM code into a +// This file defines the interfaces that RISC-V uses to lower LLVM code into a // selection DAG. // //===----------------------------------------------------------------------===// @@ -2090,7 +2090,7 @@ static SDValue lowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { - // RISCV FP-to-int conversions saturate to the destination register size, but + // RISC-V FP-to-int conversions saturate to the destination register size, but // don't produce 0 for nan. We can use a conversion instruction and fix the // nan case with a compare and a select. SDValue Src = Op.getOperand(0); @@ -7979,8 +7979,8 @@ SDVTList VTs = DAG.getVTList(XLenVT, MVT::Other); SDValue RM = DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo); - // Encoding used for rounding mode in RISCV differs from that used in - // FLT_ROUNDS. To convert it the RISCV rounding mode is used as an index in a + // Encoding used for rounding mode in RISC-V differs from that used in + // FLT_ROUNDS. To convert it the RISC-V rounding mode is used as an index in a // table, which consists of a sequence of 4-bit fields, each representing // corresponding FLT_ROUNDS mode. static const int Table = @@ -8009,10 +8009,10 @@ SDValue SysRegNo = DAG.getTargetConstant( RISCVSysReg::lookupSysRegByName("FRM")->Encoding, DL, XLenVT); - // Encoding used for rounding mode in RISCV differs from that used in + // Encoding used for rounding mode in RISC-V differs from that used in // FLT_ROUNDS. To convert it the C rounding mode is used as an index in // a table, which consists of a sequence of 4-bit fields, each representing - // corresponding RISCV mode. + // corresponding RISC-V mode. static const unsigned Table = (RISCVFPRndMode::RNE << 4 * int(RoundingMode::NearestTiesToEven)) | (RISCVFPRndMode::RTZ << 4 * int(RoundingMode::TowardZero)) | @@ -10286,7 +10286,7 @@ if (Opc == RISCVISD::FCVT_WU_RV64) FpToInt = DAG.getZeroExtendInReg(FpToInt, DL, MVT::i32); - // RISCV FP-to-int conversions saturate to the destination register size, but + // RISC-V FP-to-int conversions saturate to the destination register size, but // don't produce 0 for nan. SDValue ZeroInt = DAG.getConstant(0, DL, DstVT); return DAG.getSelectCC(DL, Src, Src, ZeroInt, FpToInt, ISD::CondCode::SETUO); @@ -10996,7 +10996,7 @@ } EVT IndexVT = Index.getValueType(); MVT XLenVT = Subtarget.getXLenVT(); - // RISCV indexed loads only support the "unsigned unscaled" addressing + // RISC-V indexed loads only support the "unsigned unscaled" addressing // mode, so anything else must be manually legalized. bool NeedsIdxLegalization = (IsIndexSigned && IndexVT.getVectorElementType().bitsLT(XLenVT)); @@ -14108,8 +14108,8 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { - // First, see if this is a constraint that directly corresponds to a - // RISCV register class. + // First, see if this is a constraint that directly corresponds to a RISC-V + // register class. if (Constraint.size() == 1) { switch (Constraint[0]) { case 'r': Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h =================================================================== --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -1,4 +1,4 @@ -//===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISCV ------===// +//===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V -----===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file defines an instruction selector for the RISCV target. +// This file defines an instruction selector for the RISC-V target. // //===----------------------------------------------------------------------===// @@ -18,7 +18,7 @@ #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Support/KnownBits.h" -// RISCV-specific code to select RISCV machine instructions for +// RISC-V specific code to select RISC-V machine instructions for // SelectionDAG operations. namespace llvm { class RISCVDAGToDAGISel : public SelectionDAGISel { Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -1,4 +1,4 @@ -//===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===// +//===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISC-V -----===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file defines an instruction selector for the RISCV target. +// This file defines an instruction selector for the RISC-V target. // //===----------------------------------------------------------------------===// @@ -2363,7 +2363,7 @@ SDValue &ShAmt) { ShAmt = N; - // Shift instructions on RISCV only read the lower 5 or 6 bits of the shift + // Shift instructions on RISC-V only read the lower 5 or 6 bits of the shift // amount. If there is an AND on the shift amount, we can bypass it if it // doesn't affect any of those bits. if (ShAmt.getOpcode() == ISD::AND && isa<ConstantSDNode>(ShAmt.getOperand(1))) { Index: llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp +++ llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // // This pass custom lowers llvm.gather and llvm.scatter instructions to -// RISCV intrinsics. +// RISC-V intrinsics. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVFrameLowering.h =================================================================== --- llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -1,4 +1,4 @@ -//===-- RISCVFrameLowering.h - Define frame lowering for RISCV -*- C++ -*--===// +//===-- RISCVFrameLowering.h - Define frame lowering for RISC-V -*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This class implements RISCV-specific bits of TargetFrameLowering class. +// This class implements RISC-V specific bits of TargetFrameLowering class. // //===----------------------------------------------------------------------===// @@ -74,7 +74,7 @@ TargetStackID::Value getStackIDForScalableVectors() const override; bool isStackIdSafeForLocalArea(unsigned StackId) const override { - // We don't support putting RISCV Vector objects into the pre-allocated + // We don't support putting RISC-V Vector objects into the pre-allocated // local frame block at the moment. return StackId != TargetStackID::ScalableVector; } Index: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -1,4 +1,4 @@ -//===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===// +//===-- RISCVFrameLowering.cpp - RISC-V Frame Information -----------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the RISCV implementation of TargetFrameLowering class. +// This file contains the RISC-V implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVFeatures.td =================================================================== --- llvm/lib/Target/RISCV/RISCVFeatures.td +++ llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1,4 +1,4 @@ -//===-- RISCVFeatures.td - RISCV Features and Extensions ---*- tablegen -*-===// +//===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp +++ llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This is a RISCV specific version of CodeGenPrepare. +// This is a RISC-V specific version of CodeGenPrepare. // It munges the code in the input function to better prepare it for // SelectionDAG-based code generation. This works around limitations in it's // basic-block-at-a-time approach. Index: llvm/lib/Target/RISCV/RISCVCallingConv.td =================================================================== --- llvm/lib/Target/RISCV/RISCVCallingConv.td +++ llvm/lib/Target/RISCV/RISCVCallingConv.td @@ -1,4 +1,4 @@ -//===-- RISCVCallingConv.td - Calling Conventions RISCV ----*- tablegen -*-===// +//===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This describes the calling conventions for the RISCV architecture. +// This describes the calling conventions for the RISC-V architecture. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -1,4 +1,4 @@ -//===-- RISCVAsmPrinter.cpp - RISCV LLVM assembly writer ------------------===// +//===-- RISCVAsmPrinter.cpp - RISC-V LLVM assembly writer -----------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // // This file contains a printer that converts from our internal representation -// of machine-dependent LLVM code to the RISCV assembly language. +// of machine-dependent LLVM code to the RISC-V assembly language. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCV.td =================================================================== --- llvm/lib/Target/RISCV/RISCV.td +++ llvm/lib/Target/RISCV/RISCV.td @@ -1,4 +1,4 @@ -//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===// +//===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/RISCV.h =================================================================== --- llvm/lib/Target/RISCV/RISCV.h +++ llvm/lib/Target/RISCV/RISCV.h @@ -1,4 +1,4 @@ -//===-- RISCV.h - Top-level interface for RISCV -----------------*- C++ -*-===// +//===-- RISCV.h - Top-level interface for RISC-V ----------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h @@ -1,4 +1,4 @@ -//===-- RISCVTargetStreamer.h - RISCV Target Streamer ----------*- C++ -*--===// +//===-- RISCVTargetStreamer.h - RISC-V Target Streamer ---------*- C++ -*--===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -1,4 +1,4 @@ -//===-- RISCVTargetStreamer.cpp - RISCV Target Streamer Methods -----------===// +//===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file provides RISCV specific target streamer methods. +// This file provides RISC-V specific target streamer methods. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h @@ -1,4 +1,4 @@ -//===-- RISCVMCTargetDesc.h - RISCV Target Descriptions ---------*- C++ -*-===// +//===-- RISCVMCTargetDesc.h - RISC-V Target Descriptions --------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file provides RISCV specific target descriptions. +// This file provides RISC-V specific target descriptions. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp @@ -1,4 +1,4 @@ -//===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===// +//===-- RISCVMCTargetDesc.cpp - RISC-V Target Descriptions ----------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// -/// This file provides RISCV-specific target descriptions. +/// This file provides RISC-V specific target descriptions. /// //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.h @@ -1,4 +1,4 @@ -//===-- RISCVMCObjectFileInfo.h - RISCV object file Info -------*- C++ -*--===// +//===-- RISCVMCObjectFileInfo.h - RISC-V object file Info ------*- C++ -*--===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp @@ -1,4 +1,4 @@ -//===-- RISCVMCObjectFileInfo.cpp - RISCV object file properties ----------===// +//===-- RISCVMCObjectFileInfo.cpp - RISC-V object file properties ---------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h @@ -1,4 +1,4 @@ -//===-- RISCVMCExpr.h - RISCV specific MC expression classes ----*- C++ -*-===// +//===-- RISCVMCExpr.h - RISC-V specific MC expression classes----*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file describes RISCV-specific MCExprs, used for modifiers like +// This file describes RISC-V specific MCExprs, used for modifiers like // "%hi" or "%lo" etc., // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp @@ -1,4 +1,4 @@ -//===-- RISCVMCExpr.cpp - RISCV specific MC expression classes ------------===// +//===-- RISCVMCExpr.cpp - RISC-V specific MC expression classes -----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // // This file contains the implementation of the assembly expression modifiers -// accepted by the RISCV architecture (e.g. ":lo12:", ":gottprel_g1:", ...). +// accepted by the RISC-V architecture (e.g. ":lo12:", ":gottprel_g1:", ...). // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -1,4 +1,4 @@ -//===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===// +//===-- RISCVMCCodeEmitter.cpp - Convert RISC-V code to machine code ------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -98,7 +98,7 @@ // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with // relocation types. We expand those pseudo-instructions while encoding them, -// meaning AUIPC and JALR won't go through RISCV MC to MC compressed +// meaning AUIPC and JALR won't go through RISC-V MC to MC compressed // instruction transformation. This is acceptable because AUIPC has no 16-bit // form and C_JALR has no immediate operand field. We let linker relaxation // deal with it. When linker relaxation is enabled, AUIPC and JALR have a Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.h @@ -1,4 +1,4 @@ -//===-- RISCVMCAsmInfo.h - RISCV Asm Info ----------------------*- C++ -*--===// +//===-- RISCVMCAsmInfo.h - RISC-V Asm Info ---------------------*- C++ -*--===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp @@ -1,4 +1,4 @@ -//===-- RISCVMCAsmInfo.cpp - RISCV Asm properties -------------------------===// +//===-- RISCVMCAsmInfo.cpp - RISC-V Asm properties ------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -1,4 +1,4 @@ -//===-- RISCVInstPrinter.h - Convert RISCV MCInst to asm syntax ---*- C++ -*--// +//===-- RISCVInstPrinter.h - Convert RISC-V MCInst to asm syntax --*- C++ -*--// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This class prints a RISCV MCInst to a .s file. +// This class prints a RISC-V MCInst to a .s file. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -1,4 +1,4 @@ -//===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===// +//===-- RISCVInstPrinter.cpp - Convert RISC-V MCInst to asm syntax --------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This class prints an RISCV MCInst to a .s file. +// This class prints an RISC-V MCInst to a .s file. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h @@ -1,4 +1,4 @@ -//===-- RISCVELFStreamer.h - RISCV ELF Target Streamer ---------*- C++ -*--===// +//===-- RISCVELFStreamer.h - RISC-V ELF Target Streamer ---------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp @@ -1,4 +1,4 @@ -//===-- RISCVELFStreamer.cpp - RISCV ELF Target Streamer Methods ----------===// +//===-- RISCVELFStreamer.cpp - RISC-V ELF Target Streamer Methods ---------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file provides RISCV specific target streamer methods. +// This file provides RISC-V specific target streamer methods. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp @@ -1,4 +1,4 @@ -//===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===// +//===-- RISCVELFObjectWriter.cpp - RISC-V ELF Writer ----------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -1,4 +1,4 @@ -//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===// +//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains small standalone enum definitions for the RISCV target +// This file contains small standalone enum definitions for the RISC-V target // useful for the compiler back-end and the MC libraries. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -1,4 +1,4 @@ -//===-- RISCVBaseInfo.cpp - Top level definitions for RISCV MC ------------===// +//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains small standalone enum definitions for the RISCV target +// This file contains small standalone enum definitions for the RISC-V target // useful for the compiler back-end and the MC libraries. // //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h @@ -1,4 +1,4 @@ -//===-- RISCVAsmBackend.h - RISCV Assembler Backend -----------------------===// +//===-- RISCVAsmBackend.h - RISC-V Assembler Backend ----------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h =================================================================== --- llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h +++ llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h @@ -46,7 +46,7 @@ bool shouldIgnoreInstruments() const override { return false; } bool supportsInstrumentType(StringRef Type) const override; - /// Create a Instrument for RISCV target + /// Create a Instrument for RISC-V target SharedInstrument createInstrument(StringRef Desc, StringRef Data) override; /// Using the Instrument, returns a SchedClassID to use instead of Index: llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp =================================================================== --- llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -56,7 +56,7 @@ // below assert(isDataValid(getData()) && "Cannot get LMUL because invalid Data value"); - // These are the LMUL values that are used in RISCV tablegen + // These are the LMUL values that are used in RISC-V tablegen return StringSwitch<uint8_t>(getData()) .Case("M1", 0b000) .Case("M2", 0b001) @@ -139,7 +139,7 @@ return new RISCVInstrumentManager(STI, MCII); } -/// Extern function to initialize the targets for the RISCV backend +/// Extern function to initialize the targets for the RISC-V backend extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMCA() { TargetRegistry::RegisterInstrumentManager(getTheRISCV32Target(), createRISCVInstrumentManager); Index: llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td =================================================================== --- llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td +++ llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td @@ -1,4 +1,4 @@ -//=-- RISCVRegisterBank.td - Describe the RISCV Banks --------*- tablegen -*-=// +//=-- RISCVRegisterBank.td - Describe the RISC-V Banks -------*- tablegen -*-=// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h =================================================================== --- llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h +++ llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file declares the targeting of the RegisterBankInfo class for RISCV. +/// This file declares the targeting of the RegisterBankInfo class for RISC-V. /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp +++ llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file implements the targeting of the RegisterBankInfo class for RISCV. +/// This file implements the targeting of the RegisterBankInfo class for RISC-V. /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h =================================================================== --- llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h +++ llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file declares the targeting of the Machinelegalizer class for RISCV. +/// This file declares the targeting of the Machinelegalizer class for RISC-V. /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +++ llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file implements the targeting of the Machinelegalizer class for RISCV. +/// This file implements the targeting of the Machinelegalizer class for RISC-V. /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp =================================================================== --- llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// /// \file /// This file implements the targeting of the InstructionSelector class for -/// RISCV. +/// RISC-V. /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp =================================================================== --- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -1,4 +1,4 @@ -//===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===// +//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp =================================================================== --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1,4 +1,4 @@ -//===-- RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions --===// +//===-- RISCVAsmParser.cpp - Parse RISC-V assembly to MCInst instructions -===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/lib/Support/RISCVISAInfo.cpp =================================================================== --- llvm/lib/Support/RISCVISAInfo.cpp +++ llvm/lib/Support/RISCVISAInfo.cpp @@ -1,4 +1,4 @@ -//===-- RISCVISAInfo.cpp - RISCV Arch String Parser -------------*- C++ -*-===// +//===-- RISCVISAInfo.cpp - RISC-V Arch String Parser ------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: llvm/include/llvm/TargetParser/RISCVTargetParser.h =================================================================== --- llvm/include/llvm/TargetParser/RISCVTargetParser.h +++ llvm/include/llvm/TargetParser/RISCVTargetParser.h @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // // This file implements a target parser to recognise hardware features -// FOR RISC-V CPUS. +// for RISC-V CPUs. // //===----------------------------------------------------------------------===// Index: llvm/include/llvm/Support/RISCVISAInfo.h =================================================================== --- llvm/include/llvm/Support/RISCVISAInfo.h +++ llvm/include/llvm/Support/RISCVISAInfo.h @@ -1,4 +1,4 @@ -//===-- RISCVISAInfo.h - RISCV ISA Information ------------------*- C++ -*-===// +//===-- RISCVISAInfo.h - RISC-V ISA Information -----------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -44,23 +44,23 @@ RISCVISAInfo(unsigned XLen, OrderedExtensionMap &Exts) : XLen(XLen), FLen(0), MinVLen(0), MaxELen(0), MaxELenFp(0), Exts(Exts) {} - /// Parse RISCV ISA info from arch string. + /// Parse RISC-V ISA info from arch string. static llvm::Expected<std::unique_ptr<RISCVISAInfo>> parseArchString(StringRef Arch, bool EnableExperimentalExtension, bool ExperimentalExtensionVersionCheck = true, bool IgnoreUnknown = false); - /// Parse RISCV ISA info from an arch string that is already in normalized + /// Parse RISC-V ISA info from an arch string that is already in normalized /// form (as defined in the psABI). Unlike parseArchString, this function /// will not error for unrecognized extension names or extension versions. static llvm::Expected<std::unique_ptr<RISCVISAInfo>> parseNormalizedArchString(StringRef Arch); - /// Parse RISCV ISA info from feature vector. + /// Parse RISC-V ISA info from feature vector. static llvm::Expected<std::unique_ptr<RISCVISAInfo>> parseFeatures(unsigned XLen, const std::vector<std::string> &Features); - /// Convert RISCV ISA info to a feature vector. + /// Convert RISC-V ISA info to a feature vector. void toFeatures(std::vector<StringRef> &Features, llvm::function_ref<StringRef(const Twine &)> StrAlloc, bool AddAllExtensions) const; Index: lld/ELF/InputSection.cpp =================================================================== --- lld/ELF/InputSection.cpp +++ lld/ELF/InputSection.cpp @@ -724,7 +724,7 @@ p = p & 0xfffffffc; if (sym.isUndefined()) { // On ARM and AArch64 a branch to an undefined weak resolves to the next - // instruction, otherwise the place. On RISCV, resolve an undefined weak + // instruction, otherwise the place. On RISC-V, resolve an undefined weak // to the same instruction to cause an infinite loop (making the user // aware of the issue) while ensuring no overflow. // Note: if the symbol is hidden, its binding has been converted to local, Index: compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h =================================================================== --- compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h +++ compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h @@ -91,10 +91,10 @@ #elif defined(__sparc__) || defined(__mips__) return pc - 8; #elif SANITIZER_RISCV64 - // RV-64 has variable instruciton length... + // RV-64 has variable instruction length... // C extentions gives us 2-byte instructoins // RV-64 has 4-byte instructions - // + RISCV architecture allows instructions up to 8 bytes + // + RISC-V architecture allows instructions up to 8 bytes // It seems difficult to figure out the exact instruction length - // pc - 2 seems like a safe option for the purposes of stack tracing return pc - 2; Index: clang/lib/Driver/ToolChains/RISCVToolchain.h =================================================================== --- clang/lib/Driver/ToolChains/RISCVToolchain.h +++ clang/lib/Driver/ToolChains/RISCVToolchain.h @@ -1,4 +1,4 @@ -//===--- RISCVToolchain.h - RISCV ToolChain Implementations -----*- C++ -*-===// +//===--- RISCVToolchain.h - RISC-V ToolChain Implementations ----*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: clang/lib/Driver/ToolChains/RISCVToolchain.cpp =================================================================== --- clang/lib/Driver/ToolChains/RISCVToolchain.cpp +++ clang/lib/Driver/ToolChains/RISCVToolchain.cpp @@ -1,4 +1,4 @@ -//===--- RISCVToolchain.cpp - RISCV ToolChain Implementations ---*- C++ -*-===// +//===--- RISCVToolchain.cpp - RISC-V ToolChain Implementations --*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -46,7 +46,7 @@ return llvm::sys::fs::exists(GCCDir); } -/// RISCV Toolchain +/// RISC-V Toolchain RISCVToolChain::RISCVToolChain(const Driver &D, const llvm::Triple &Triple, const ArgList &Args) : Generic_ELF(D, Triple, Args) { Index: clang/lib/Driver/ToolChains/Arch/RISCV.h =================================================================== --- clang/lib/Driver/ToolChains/Arch/RISCV.h +++ clang/lib/Driver/ToolChains/Arch/RISCV.h @@ -1,4 +1,4 @@ -//===--- RISCV.h - RISCV-specific Tool Helpers ------------------*- C++ -*-===// +//===--- RISCV.h - RISC-V-specific Tool Helpers -----------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp =================================================================== --- clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -1,4 +1,4 @@ -//===--- RISCV.cpp - RISCV Helpers for Tools --------------------*- C++ -*-===// +//===--- RISCV.cpp - RISC-V Helpers for Tools -------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. Index: clang/lib/CodeGen/TargetInfo.cpp =================================================================== --- clang/lib/CodeGen/TargetInfo.cpp +++ clang/lib/CodeGen/TargetInfo.cpp @@ -11053,7 +11053,7 @@ return nullptr; } //===----------------------------------------------------------------------===// -// RISCV ABI Implementation +// RISC-V ABI Implementation //===----------------------------------------------------------------------===// namespace { Index: clang/lib/Basic/Targets/RISCV.h =================================================================== --- clang/lib/Basic/Targets/RISCV.h +++ clang/lib/Basic/Targets/RISCV.h @@ -1,4 +1,4 @@ -//===--- RISCV.h - Declare RISCV target feature support ---------*- C++ -*-===// +//===--- RISCV.h - Declare RISC-V target feature support --------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file declares RISCV TargetInfo objects. +// This file declares RISC-V TargetInfo objects. // //===----------------------------------------------------------------------===// Index: clang/lib/Basic/Targets/RISCV.cpp =================================================================== --- clang/lib/Basic/Targets/RISCV.cpp +++ clang/lib/Basic/Targets/RISCV.cpp @@ -1,4 +1,4 @@ -//===--- RISCV.cpp - Implement RISCV target feature support ---------------===// +//===--- RISCV.cpp - Implement RISC-V target feature support --------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file implements RISCV TargetInfo objects. +// This file implements RISC-V TargetInfo objects. // //===----------------------------------------------------------------------===//
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