[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

[sstwcw via Phabricator via cfe-commits]

sstwcw added inline comments.


================
Comment at: clang/lib/Format/TokenAnnotator.cpp:2665
+    if (Style.isVerilog() && Precedence == prec::Comma &&
+        VerilogFirstOfType != nullptr) {
+      addFakeParenthesis(VerilogFirstOfType, prec::Comma);
----------------
owenpan wrote:
> And other places as well.
@HazardyKnusperkeks Do you agree?  I remember you once said you preferred the 
`nullptr` style.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143825/new/

https://reviews.llvm.org/D143825

_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits