Author: Jun Ma Date: 2023-02-17T09:17:47+08:00 New Revision: e073de833671159f89d72a1018d4444335cc042d
URL: https://github.com/llvm/llvm-project/commit/e073de833671159f89d72a1018d4444335cc042d DIFF: https://github.com/llvm/llvm-project/commit/e073de833671159f89d72a1018d4444335cc042d.diff LOG: [WebAssembly] Update wasm.c with update_cc_test_checks.py. NFC Added: Modified: clang/test/Headers/wasm.c Removed: ################################################################################ diff --git a/clang/test/Headers/wasm.c b/clang/test/Headers/wasm.c index 8913a273aaeb1..42e11e412ea4a 100644 --- a/clang/test/Headers/wasm.c +++ b/clang/test/Headers/wasm.c @@ -1,4 +1,4 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --force-update +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: webassembly-registered-target, asserts // FIXME: This should not be using -O2 and implicitly testing the entire IR opt pipeline. @@ -1462,8 +1462,8 @@ v128_t test_f64x2_ge(v128_t a, v128_t b) { // CHECK-LABEL: @test_v128_not( // CHECK-NEXT: entry: -// CHECK-NEXT: [[NEG_I:%.*]] = xor <4 x i32> [[A:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1> -// CHECK-NEXT: ret <4 x i32> [[NEG_I]] +// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i32> [[A:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1> +// CHECK-NEXT: ret <4 x i32> [[NOT_I]] // v128_t test_v128_not(v128_t a) { return wasm_v128_not(a); @@ -1498,8 +1498,8 @@ v128_t test_v128_xor(v128_t a, v128_t b) { // CHECK-LABEL: @test_v128_andnot( // CHECK-NEXT: entry: -// CHECK-NEXT: [[NEG_I:%.*]] = xor <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1> -// CHECK-NEXT: [[AND_I:%.*]] = and <4 x i32> [[NEG_I]], [[A:%.*]] +// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1> +// CHECK-NEXT: [[AND_I:%.*]] = and <4 x i32> [[NOT_I]], [[A:%.*]] // CHECK-NEXT: ret <4 x i32> [[AND_I]] // v128_t test_v128_andnot(v128_t a, v128_t b) { @@ -1529,9 +1529,9 @@ v128_t test_v128_bitselect(v128_t a, v128_t b, v128_t mask) { // CHECK-LABEL: @test_i8x16_abs( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x i8> @llvm.abs.v16i8(<16 x i8> [[TMP0]], i1 false) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// CHECK-NEXT: [[ABS_I:%.*]] = tail call <16 x i8> @llvm.abs.v16i8(<16 x i8> [[TMP0]], i1 false) +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[ABS_I]] to <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] // v128_t test_i8x16_abs(v128_t a) { return wasm_i8x16_abs(a); @@ -1757,9 +1757,9 @@ v128_t test_u8x16_avgr(v128_t a, v128_t b) { // CHECK-LABEL: @test_i16x8_abs( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> -// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.abs.v8i16(<8 x i16> [[TMP0]], i1 false) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// CHECK-NEXT: [[ABS_I:%.*]] = tail call <8 x i16> @llvm.abs.v8i16(<8 x i16> [[TMP0]], i1 false) +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[ABS_I]] to <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] // v128_t test_i16x8_abs(v128_t a) { return wasm_i16x8_abs(a); @@ -1985,8 +1985,8 @@ v128_t test_u16x8_avgr(v128_t a, v128_t b) { // CHECK-LABEL: @test_i32x4_abs( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[A:%.*]], i1 false) -// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// CHECK-NEXT: [[ABS_I:%.*]] = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[A:%.*]], i1 false) +// CHECK-NEXT: ret <4 x i32> [[ABS_I]] // v128_t test_i32x4_abs(v128_t a) { return wasm_i32x4_abs(a); @@ -2130,9 +2130,9 @@ v128_t test_i32x4_dot_i16x8(v128_t a, v128_t b) { // CHECK-LABEL: @test_i64x2_abs( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <2 x i64> -// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.abs.v2i64(<2 x i64> [[TMP0]], i1 false) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// CHECK-NEXT: [[ABS_I:%.*]] = tail call <2 x i64> @llvm.abs.v2i64(<2 x i64> [[TMP0]], i1 false) +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[ABS_I]] to <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] // v128_t test_i64x2_abs(v128_t a) { return wasm_i64x2_abs(a); _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
