paulwalker-arm added inline comments.
================ Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:6361 + def : SVE_2_Op_Pat<nxv4i1, ir_op, nxv4i1, nxv4i1, !cast<Instruction>(NAME # _S)>; + def : SVE_2_Op_Pat<nxv2i1, ir_op, nxv2i1, nxv2i1, !cast<Instruction>(NAME # _D)>; } ---------------- peterwaller-arm wrote: > Out of interest, is there a good reason to handle the nxv16 pattern case > differently in the `I` multiclass args? Written this way at a glance it looks > like it is missing. My reasoning was the pattern within the instruction class is mandatory for the correct clang builtin support so I figured that should take priority. That means extra patterns are only required for the unpacked cases, which are optional based on them having value during code generation. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142065/new/ https://reviews.llvm.org/D142065 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
