[PATCH] D141032: [Clang][RISCV] Expose vlenb to vread_csr

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: craig.topper, kito-cheng, frasercrmck.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

This commit resolves: riscv-non-isa/rvv-intrinsic-doc#180


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141032

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
@@ -40,3 +40,12 @@
 unsigned long vread_csr_vcsr(void) {
   return vread_csr(RVV_VCSR);
 }
+
+// CHECK-LABEL: @vread_csr_vlenb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, 
vlenb", "=r,~{memory}"() #[[ATTR1]], !srcloc !8
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vlenb(void) {
+  return vread_csr(RVV_VLENB);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===================================================================
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1516,6 +1516,7 @@
   RVV_VXSAT,
   RVV_VXRM,
   RVV_VCSR,
+  RVV_VLENB,
 };
 
 static __inline__ __attribute__((__always_inline__, __nodebug__))
@@ -1534,6 +1535,9 @@
     case RVV_VCSR:
       __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
       break;
+    case RVV_VLENB:
+      __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+      break;
   }
   return __rv;
 }



Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
@@ -40,3 +40,12 @@
 unsigned long vread_csr_vcsr(void) {
   return vread_csr(RVV_VCSR);
 }
+
+// CHECK-LABEL: @vread_csr_vlenb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vlenb", "=r,~{memory}"() #[[ATTR1]], !srcloc !8
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vlenb(void) {
+  return vread_csr(RVV_VLENB);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===================================================================
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1516,6 +1516,7 @@
   RVV_VXSAT,
   RVV_VXRM,
   RVV_VCSR,
+  RVV_VLENB,
 };
 
 static __inline__ __attribute__((__always_inline__, __nodebug__))
@@ -1534,6 +1535,9 @@
     case RVV_VCSR:
       __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
       break;
+    case RVV_VLENB:
+      __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+      break;
   }
   return __rv;
 }

_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits