Author: Craig Topper Date: 2022-11-02T13:09:14-07:00 New Revision: 6254495c6b4f35ad862c9a5fc28720664d28d816
URL: https://github.com/llvm/llvm-project/commit/6254495c6b4f35ad862c9a5fc28720664d28d816 DIFF: https://github.com/llvm/llvm-project/commit/6254495c6b4f35ad862c9a5fc28720664d28d816.diff LOG: [RISCV] Move RVVBitsPerBlock to TargetParser.h so we can use it in clang. NFC Differential Revision: https://reviews.llvm.org/D137266 Added: Modified: clang/lib/Basic/Targets/RISCV.cpp llvm/include/llvm/Support/TargetParser.h llvm/lib/Target/RISCV/RISCVISelLowering.h Removed: ################################################################################ diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 08da01602599..36fa96274982 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -255,7 +255,8 @@ RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const { if (unsigned MinVLen = ISAInfo->getMinVLen()) { unsigned MaxVLen = ISAInfo->getMaxVLen(); // RISCV::RVVBitsPerBlock is 64. - return std::pair<unsigned, unsigned>(MinVLen/64, MaxVLen/64); + return std::make_pair(MinVLen / llvm::RISCV::RVVBitsPerBlock, + MaxVLen / llvm::RISCV::RVVBitsPerBlock); } return None; diff --git a/llvm/include/llvm/Support/TargetParser.h b/llvm/include/llvm/Support/TargetParser.h index e9920a50bae8..39222b02e21a 100644 --- a/llvm/include/llvm/Support/TargetParser.h +++ b/llvm/include/llvm/Support/TargetParser.h @@ -157,6 +157,9 @@ IsaVersion getIsaVersion(StringRef GPU); namespace RISCV { +// We use 64 bits as the known part in the scalable vector types. +static constexpr unsigned RVVBitsPerBlock = 64; + enum CPUKind : unsigned { #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM, #define TUNE_PROC(ENUM, NAME) CK_##ENUM, diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 1b8a4c557afa..4f07d9ece8f3 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -18,6 +18,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLowering.h" +#include "llvm/Support/TargetParser.h" namespace llvm { class RISCVSubtarget; @@ -325,11 +326,6 @@ enum NodeType : unsigned { }; } // namespace RISCVISD -namespace RISCV { -// We use 64 bits as the known part in the scalable vector types. -static constexpr unsigned RVVBitsPerBlock = 64; -} // namespace RISCV - class RISCVTargetLowering : public TargetLowering { const RISCVSubtarget &Subtarget; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
