dmgreen added inline comments.
================
Comment at: llvm/lib/Support/Host.cpp:216
.Case("0xd41", "cortex-a78")
+ .Case("0xd00", "cortex-a715")
.Case("0xd44", "cortex-x1")
----------------
Should be 0xd4d I think, according to the MIDR in the TRM.
================
Comment at: llvm/lib/Target/AArch64/AArch64.td:771
+ FeaturePostRAScheduler,
+ FeatureCmpBccFusion]>;
+
----------------
Please add FeatureLSLFast and FeatureFuseAdrpAdd.
================
Comment at: llvm/lib/Target/AArch64/AArch64.td:1244
[TuneA710]>;
+def : ProcessorModel<"cortex-a715", CortexA57Model, ProcessorFeatures.A715,
+ [TuneA715]>;
----------------
This can use NeoverseN2Model.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D136957/new/
https://reviews.llvm.org/D136957
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