craig.topper added inline comments.
================ Comment at: llvm/lib/Target/X86/X86.td:259 + "Support RAO-INT instructions", + [FeatureSSE2]>; def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", ---------------- pengfei wrote: > craig.topper wrote: > > Why do these require SSE2? > We need mfence instructions for strong orders. The mfence feature relies on > SSE2. > I see your concern, we may need split these features from SSE2. Filed an > issue https://github.com/llvm/llvm-project/issues/58388 The lowering code for atomics could check SSE2 in addition to the RAO-INT feature. My primary concern was that the RAO-INT feature itself shouldn't require it. Are there going to be intrinsics for RAO-INT? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D135951/new/ https://reviews.llvm.org/D135951 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
