bob80905 added a comment. In D135011#3831452 <https://reviews.llvm.org/D135011#3831452>, @craig.topper wrote:
> Does these support scalable vector types from ARM SVE or RISC-V? I can't > remember what the rest of the __builtin_elementwise do. I ask because the > backends will probably crash for them. I sat with @beanz and looked at the assembly code generated for the riscv64-unknown-elf target and the aarch64-apple-darwin target. The compiler doesn't crash. The generated assembly looks good, there are 4 sinf calls, one generated for each element in the vector. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D135011/new/ https://reviews.llvm.org/D135011 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
