Carrot created this revision.
Carrot added a reviewer: dmgreen.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
Carrot requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.
Reserved physical registers can't be assigned to virtual registers, but they
can still be used as ABI required. So we can reserve X8, X16, X17 and X19.
Similarly argument registers can be reserved even if they are used by function
call.
With this change we can reserve most of the physical registers, it is much
easier to test and debug register allocator.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D132531
Files:
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64FastISel.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.h
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
llvm/test/CodeGen/AArch64/arm64-platform-reg.ll
llvm/test/CodeGen/AArch64/arm64-reserved-arg-reg-call-error.ll
Index: llvm/test/CodeGen/AArch64/arm64-reserved-arg-reg-call-error.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-reserved-arg-reg-call-error.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; RUN: not llc < %s -mtriple=arm64-linux-gnu -mattr=+reserve-x1 2>&1 | FileCheck %s
-; RUN: not llc < %s -mtriple=arm64-linux-gnu -mattr=+reserve-x1 -fast-isel 2>&1 | FileCheck %s
-; RUN: not llc < %s -mtriple=arm64-linux-gnu -mattr=+reserve-x1 -global-isel 2>&1 | FileCheck %s
-
-; CHECK: error:
-; CHECK-SAME: AArch64 doesn't support function calls if any of the argument registers is reserved.
-define void @call_function() {
- call void @foo()
- ret void
-}
-declare void @foo()
-
-; CHECK: error:
-; CHECK-SAME: AArch64 doesn't support function calls if any of the argument registers is reserved.
-define void @call_memcpy(i8* %out, i8* %in) {
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 800, i1 false)
- ret void
-}
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i1)
Index: llvm/test/CodeGen/AArch64/arm64-platform-reg.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-platform-reg.ll
+++ llvm/test/CodeGen/AArch64/arm64-platform-reg.ll
@@ -13,6 +13,7 @@
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x5 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X5
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x6 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X6
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x7 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X7
+; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x8 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X8
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x9 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X9
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x10 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X10
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x11 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X11
@@ -20,6 +21,9 @@
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x13 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X13
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x14 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X14
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x15 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X15
+; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x16 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X16
+; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x17 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X17
+; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x19 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X19
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x20 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X20
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x21 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X21
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x22 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X22
@@ -51,6 +55,7 @@
; RUN: -mattr=+reserve-x5 \
; RUN: -mattr=+reserve-x6 \
; RUN: -mattr=+reserve-x7 \
+; RUN: -mattr=+reserve-x8 \
; RUN: -mattr=+reserve-x9 \
; RUN: -mattr=+reserve-x10 \
; RUN: -mattr=+reserve-x11 \
@@ -58,7 +63,10 @@
; RUN: -mattr=+reserve-x13 \
; RUN: -mattr=+reserve-x14 \
; RUN: -mattr=+reserve-x15 \
+; RUN: -mattr=+reserve-x16 \
+; RUN: -mattr=+reserve-x17 \
; RUN: -mattr=+reserve-x18 \
+; RUN: -mattr=+reserve-x19 \
; RUN: -mattr=+reserve-x20 \
; RUN: -mattr=+reserve-x21 \
; RUN: -mattr=+reserve-x22 \
@@ -78,6 +86,7 @@
; RUN: --check-prefix=CHECK-RESERVE-X5 \
; RUN: --check-prefix=CHECK-RESERVE-X6 \
; RUN: --check-prefix=CHECK-RESERVE-X7 \
+; RUN: --check-prefix=CHECK-RESERVE-X8 \
; RUN: --check-prefix=CHECK-RESERVE-X9 \
; RUN: --check-prefix=CHECK-RESERVE-X10 \
; RUN: --check-prefix=CHECK-RESERVE-X11 \
@@ -85,7 +94,10 @@
; RUN: --check-prefix=CHECK-RESERVE-X13 \
; RUN: --check-prefix=CHECK-RESERVE-X14 \
; RUN: --check-prefix=CHECK-RESERVE-X15 \
+; RUN: --check-prefix=CHECK-RESERVE-X16 \
+; RUN: --check-prefix=CHECK-RESERVE-X17 \
; RUN: --check-prefix=CHECK-RESERVE-X18 \
+; RUN: --check-prefix=CHECK-RESERVE-X19 \
; RUN: --check-prefix=CHECK-RESERVE-X20 \
; RUN: --check-prefix=CHECK-RESERVE-X21 \
; RUN: --check-prefix=CHECK-RESERVE-X22 \
@@ -113,6 +125,8 @@
; CHECK: str x18
; CHECK-RESERVE-NOT: ldr fp
+; CHECK-RESERVE-X8-NOT: adrp x8
+; CHECK-RESERVE-X8-NOT: ldr x8
; CHECK-RESERVE-X1-NOT: ldr x1,
; CHECK-RESERVE-X2-NOT: ldr x2,
; CHECK-RESERVE-X3-NOT: ldr x3,
@@ -127,7 +141,10 @@
; CHECK-RESERVE-X13-NOT: ldr x13,
; CHECK-RESERVE-X14-NOT: ldr x14,
; CHECK-RESERVE-X15-NOT: ldr x15,
+; CHECK-RESERVE-X16-NOT: ldr x16
+; CHECK-RESERVE-X17-NOT: ldr x17
; CHECK-RESERVE-X18-NOT: ldr x18
+; CHECK-RESERVE-X19-NOT: ldr x19
; CHECK-RESERVE-X20-NOT: ldr x20
; CHECK-RESERVE-X21-NOT: ldr x21
; CHECK-RESERVE-X22-NOT: ldr x22
@@ -154,7 +171,10 @@
; CHECK-RESERVE-X13-NOT: ldr x13,
; CHECK-RESERVE-X14-NOT: ldr x14,
; CHECK-RESERVE-X15-NOT: ldr x15,
+; CHECK-RESERVE-X16-NOT: ldr x16
+; CHECK-RESERVE-X17-NOT: ldr x17
; CHECK-RESERVE-X18-NOT: ldr x18
+; CHECK-RESERVE-X19-NOT: ldr x19
; CHECK-RESERVE-X20-NOT: ldr x20
; CHECK-RESERVE-X21-NOT: ldr x21
; CHECK-RESERVE-X22-NOT: ldr x22
Index: llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -979,9 +979,6 @@
TRI->UpdateCustomCallPreservedMask(MF, &Mask);
MIB.addRegMask(Mask);
- if (TRI->isAnyArgRegReserved(MF))
- TRI->emitReservedArgRegCallError(MF);
-
// FPDiff is the byte offset of the call's argument area from the callee's.
// Stores to callee stack arguments will be placed in FixedStackSlots offset
// by this amount for a tail call. In a sibling call it must be 0 because the
@@ -1198,9 +1195,6 @@
TRI->UpdateCustomCallPreservedMask(MF, &Mask);
MIB.addRegMask(Mask);
- if (TRI->isAnyArgRegReserved(MF))
- TRI->emitReservedArgRegCallError(MF);
-
// Now we can add the actual call instruction to the correct basic block.
MIRBuilder.insertInstr(MIB);
Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.h
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterInfo.h
+++ llvm/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -35,8 +35,6 @@
}
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
- bool isAnyArgRegReserved(const MachineFunction &MF) const;
- void emitReservedArgRegCallError(const MachineFunction &MF) const;
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const;
void UpdateCustomCallPreservedMask(MachineFunction &MF,
Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -348,19 +348,6 @@
return getReservedRegs(MF)[Reg];
}
-bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {
- return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) {
- return isReservedReg(MF, r);
- });
-}
-
-void AArch64RegisterInfo::emitReservedArgRegCallError(
- const MachineFunction &MF) const {
- const Function &F = MF.getFunction();
- F.getContext().diagnose(DiagnosticInfoUnsupported{F, ("AArch64 doesn't support"
- " function calls if any of the argument registers is reserved.")});
-}
-
bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
MCRegister PhysReg) const {
return !isReservedReg(MF, PhysReg);
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6967,9 +6967,6 @@
if (Subtarget->hasCustomCallingConv())
TRI->UpdateCustomCallPreservedMask(MF, &Mask);
- if (TRI->isAnyArgRegReserved(MF))
- TRI->emitReservedArgRegCallError(MF);
-
assert(Mask && "Missing call preserved mask for calling convention");
Ops.push_back(DAG.getRegisterMask(Mask));
Index: llvm/lib/Target/AArch64/AArch64FastISel.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64FastISel.cpp
+++ llvm/lib/Target/AArch64/AArch64FastISel.cpp
@@ -3201,10 +3201,6 @@
if (!processCallArgs(CLI, OutVTs, NumBytes))
return false;
- const AArch64RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
- if (RegInfo->isAnyArgRegReserved(*MF))
- RegInfo->emitReservedArgRegCallError(*MF);
-
// Issue the call.
MachineInstrBuilder MIB;
if (Subtarget->useSmallAddressing()) {
Index: llvm/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -190,7 +190,7 @@
"Disallow all unaligned memory "
"access">;
-foreach i = {1-7,9-15,18,20-28,30} in
+foreach i = {1-28,30} in
def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
"Reserve X"#i#", making it unavailable "
"as a GPR">;
Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp
===================================================================
--- clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -518,6 +518,9 @@
if (Args.hasArg(options::OPT_ffixed_x7))
Features.push_back("+reserve-x7");
+ if (Args.hasArg(options::OPT_ffixed_x8))
+ Features.push_back("+reserve-x8");
+
if (Args.hasArg(options::OPT_ffixed_x9))
Features.push_back("+reserve-x9");
@@ -539,9 +542,18 @@
if (Args.hasArg(options::OPT_ffixed_x15))
Features.push_back("+reserve-x15");
+ if (Args.hasArg(options::OPT_ffixed_x16))
+ Features.push_back("+reserve-x16");
+
+ if (Args.hasArg(options::OPT_ffixed_x17))
+ Features.push_back("+reserve-x17");
+
if (Args.hasArg(options::OPT_ffixed_x18))
Features.push_back("+reserve-x18");
+ if (Args.hasArg(options::OPT_ffixed_x19))
+ Features.push_back("+reserve-x19");
+
if (Args.hasArg(options::OPT_ffixed_x20))
Features.push_back("+reserve-x20");
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
