kito-cheng updated this revision to Diff 442429.
kito-cheng added a comment.
Changes:
- Less invasive way to fix this issue.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D111617/new/
https://reviews.llvm.org/D111617
Files:
llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
Index: llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
===================================================================
--- llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
+++ llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
@@ -33,7 +33,7 @@
; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
; CHECK-NEXT: $x12 = ADDI $x10, 768
; CHECK-NEXT: SD killed renamable $x11, $x12, 32 :: (store (s64) into
%ir.1)
- ; CHECK-NEXT: SD $x12, $x12, 40 :: (store (s64) into %ir.2)
+ ; CHECK-NEXT: SD renamable $x10, $x12, 40 :: (store (s64) into %ir.2)
; CHECK-NEXT: renamable $x11 = ADDI $x0, 2
; CHECK-NEXT: SD killed renamable $x11, killed $x12, 48 :: (store (s64)
into %ir.3)
; CHECK-NEXT: PseudoRET
Index: llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -293,8 +293,15 @@
assert((isCompressibleLoad(MI) || isCompressibleStore(MI)) &&
"Unsupported instruction for this optimization.");
+ int SkipN = 0;
+
+ // Skip first operand for store instruction, it's operand for store value,
+ // it's unsafe to rename if offset is non-zero.
+ if (isCompressibleStore(MI) && OldRegImm.Imm != 0)
+ SkipN = 1;
+
// Update registers
- for (MachineOperand &MO : MI.operands())
+ for (MachineOperand &MO : drop_begin(MI.operands(), SkipN))
if (MO.isReg() && MO.getReg() == OldRegImm.Reg) {
// Do not update operands that define the old register.
//
Index: llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
===================================================================
--- llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
+++ llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
@@ -33,7 +33,7 @@
; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
; CHECK-NEXT: $x12 = ADDI $x10, 768
; CHECK-NEXT: SD killed renamable $x11, $x12, 32 :: (store (s64) into %ir.1)
- ; CHECK-NEXT: SD $x12, $x12, 40 :: (store (s64) into %ir.2)
+ ; CHECK-NEXT: SD renamable $x10, $x12, 40 :: (store (s64) into %ir.2)
; CHECK-NEXT: renamable $x11 = ADDI $x0, 2
; CHECK-NEXT: SD killed renamable $x11, killed $x12, 48 :: (store (s64) into %ir.3)
; CHECK-NEXT: PseudoRET
Index: llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -293,8 +293,15 @@
assert((isCompressibleLoad(MI) || isCompressibleStore(MI)) &&
"Unsupported instruction for this optimization.");
+ int SkipN = 0;
+
+ // Skip first operand for store instruction, it's operand for store value,
+ // it's unsafe to rename if offset is non-zero.
+ if (isCompressibleStore(MI) && OldRegImm.Imm != 0)
+ SkipN = 1;
+
// Update registers
- for (MachineOperand &MO : MI.operands())
+ for (MachineOperand &MO : drop_begin(MI.operands(), SkipN))
if (MO.isReg() && MO.getReg() == OldRegImm.Reg) {
// Do not update operands that define the old register.
//
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