craig.topper added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCV.td:25 + "'M' (Integer Multiplication and Division)", + [FeatureStdExtZmmul]>; def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, ---------------- This will cause Zmmul to appear in the ELF attributes any time is M is enabled. Is that what we want? ================ Comment at: llvm/test/CodeGen/RISCV/attributes.ll:76 -; RV32M: .attribute 5, "rv32i2p0_m2p0" +; RV32M: .attribute 5, "rv32i2p0_m2p0_zmmul0p1" ; RV32A: .attribute 5, "rv32i2p0_a2p0" ---------------- Is this a backwards compatibility issue? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103313/new/ https://reviews.llvm.org/D103313 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
