efriedma added a comment. In D116088#3534100 <https://reviews.llvm.org/D116088#3534100>, @kpdev42 wrote:
> 1. Sets memory barrier > 2. Calls atomic load from memory location > 3. Modifies data > 4. Calls atomic store to memory location > 5. Checks that operation is consistent, if not goes to step 2. > > Now if we are on a platform which doesn't support SMP we can use ordinary > memory operations instead > of atomic ones, can't we? Even on a non-SMP processor, there's a bit of magic in ldrex/strex: ldrex sets a hidden "lock" bit, and strex checks it. If there's a context switch between the load and the store, the switch will clear that bit. So when the code continues to execute, the store fails. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D116088/new/ https://reviews.llvm.org/D116088 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
