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It seems that we use ilp32/lp64 ABI for these archs with
only single-precision floating-point extension. I believe
that users would like to pass arguments by floating-point
registers if they provide F extension in -march. So here
we use ilp32f and lp64f for these cases.
For some existed tests, we set `-target-abi` explicitly
to keep consistent.
@benshi001 has proposed this before and I think it is
necessary.
Links:
- https://reviews.llvm.org/D103878
- https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/13
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D125947
Files:
clang/test/CodeGen/RISCV/riscv-metadata.c
clang/test/Driver/riscv-abi.c
clang/test/Driver/riscv-cpus.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
llvm/test/CodeGen/RISCV/calling-conv-half.ll
llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
llvm/test/CodeGen/RISCV/codemodel-lowering.ll
llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
llvm/test/CodeGen/RISCV/half-fcmp.ll
llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
Index: llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
+++ llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
@@ -10,8 +10,7 @@
define i32 @aext_fptosi(float %a) nounwind {
; RV64IF-LABEL: aext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = fptosi float %a to i32
ret i32 %1
@@ -20,8 +19,7 @@
define signext i32 @sext_fptosi(float %a) nounwind {
; RV64IF-LABEL: sext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = fptosi float %a to i32
ret i32 %1
@@ -30,8 +28,7 @@
define zeroext i32 @zext_fptosi(float %a) nounwind {
; RV64IF-LABEL: zext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32
; RV64IF-NEXT: ret
@@ -42,8 +39,7 @@
define i32 @aext_fptoui(float %a) nounwind {
; RV64IF-LABEL: aext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = fptoui float %a to i32
ret i32 %1
@@ -52,8 +48,7 @@
define signext i32 @sext_fptoui(float %a) nounwind {
; RV64IF-LABEL: sext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = fptoui float %a to i32
ret i32 %1
@@ -62,8 +57,7 @@
define zeroext i32 @zext_fptoui(float %a) nounwind {
; RV64IF-LABEL: zext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = fptoui float %a to i32
ret i32 %1
@@ -72,9 +66,7 @@
define i32 @bcvt_f32_to_aext_i32(float %a, float %b) nounwind {
; RV64IF-LABEL: bcvt_f32_to_aext_i32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a1
-; RV64IF-NEXT: fmv.w.x ft1, a0
-; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fadd.s ft0, fa0, fa1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = fadd float %a, %b
@@ -85,9 +77,7 @@
define signext i32 @bcvt_f32_to_sext_i32(float %a, float %b) nounwind {
; RV64IF-LABEL: bcvt_f32_to_sext_i32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a1
-; RV64IF-NEXT: fmv.w.x ft1, a0
-; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fadd.s ft0, fa0, fa1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = fadd float %a, %b
@@ -98,9 +88,7 @@
define zeroext i32 @bcvt_f32_to_zext_i32(float %a, float %b) nounwind {
; RV64IF-LABEL: bcvt_f32_to_zext_i32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a1
-; RV64IF-NEXT: fmv.w.x ft1, a0
-; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fadd.s ft0, fa0, fa1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32
@@ -115,8 +103,7 @@
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1
-; RV64IF-NEXT: fadd.s ft0, ft0, ft1
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fadd.s fa0, ft0, ft1
; RV64IF-NEXT: ret
%1 = trunc i64 %a to i32
%2 = trunc i64 %b to i32
@@ -129,8 +116,7 @@
define float @uitofp_aext_i32_to_f32(i32 %a) nounwind {
; RV64IF-LABEL: uitofp_aext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
%1 = uitofp i32 %a to float
ret float %1
@@ -139,8 +125,7 @@
define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind {
; RV64IF-LABEL: uitofp_sext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
%1 = uitofp i32 %a to float
ret float %1
@@ -149,8 +134,7 @@
define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
; RV64IF-LABEL: uitofp_zext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
%1 = uitofp i32 %a to float
ret float %1
@@ -159,8 +143,7 @@
define float @sitofp_aext_i32_to_f32(i32 %a) nounwind {
; RV64IF-LABEL: sitofp_aext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
%1 = sitofp i32 %a to float
ret float %1
@@ -169,8 +152,7 @@
define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind {
; RV64IF-LABEL: sitofp_sext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
%1 = sitofp i32 %a to float
ret float %1
@@ -179,8 +161,7 @@
define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
; RV64IF-LABEL: sitofp_zext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
%1 = sitofp i32 %a to float
ret float %1
Index: llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
+++ llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
@@ -10,8 +10,7 @@
define i32 @aext_fptosi(float %a) nounwind strictfp {
; RV64IF-LABEL: aext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
@@ -21,8 +20,7 @@
define signext i32 @sext_fptosi(float %a) nounwind strictfp {
; RV64IF-LABEL: sext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
@@ -31,8 +29,7 @@
define zeroext i32 @zext_fptosi(float %a) nounwind strictfp {
; RV64IF-LABEL: zext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32
; RV64IF-NEXT: ret
@@ -43,8 +40,7 @@
define i32 @aext_fptoui(float %a) nounwind strictfp {
; RV64IF-LABEL: aext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
@@ -54,8 +50,7 @@
define signext i32 @sext_fptoui(float %a) nounwind strictfp {
; RV64IF-LABEL: sext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
@@ -64,8 +59,7 @@
define zeroext i32 @zext_fptoui(float %a) nounwind strictfp {
; RV64IF-LABEL: zext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
@@ -74,8 +68,7 @@
define float @uitofp_aext_i32_to_f32(i32 %a) nounwind strictfp {
; RV64IF-LABEL: uitofp_aext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
@@ -85,8 +78,7 @@
define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp {
; RV64IF-LABEL: uitofp_sext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
@@ -95,8 +87,7 @@
define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp {
; RV64IF-LABEL: uitofp_zext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
@@ -105,8 +96,7 @@
define float @sitofp_aext_i32_to_f32(i32 %a) nounwind strictfp {
; RV64IF-LABEL: sitofp_aext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
@@ -116,8 +106,7 @@
define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp {
; RV64IF-LABEL: sitofp_sext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
@@ -126,8 +115,7 @@
define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp {
; RV64IF-LABEL: sitofp_zext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
Index: llvm/test/CodeGen/RISCV/half-fcmp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/half-fcmp.ll
+++ llvm/test/CodeGen/RISCV/half-fcmp.ll
@@ -4,9 +4,9 @@
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN: < %s | FileCheck -check-prefix=RV32I %s
+; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN: < %s | FileCheck -check-prefix=RV64I %s
+; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_false(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_false:
Index: llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
===================================================================
--- llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
+++ llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv32 -mattr=+zfh -target-abi=ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32IZFH %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
-; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv64 -mattr=+zfh -target-abi=lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64IZFH %s
; This file tests cases where simple floating point operations can be
Index: llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
===================================================================
--- llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
+++ llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
-; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s
; This file tests cases where simple floating point operations can be
Index: llvm/test/CodeGen/RISCV/codemodel-lowering.ll
===================================================================
--- llvm/test/CodeGen/RISCV/codemodel-lowering.ll
+++ llvm/test/CodeGen/RISCV/codemodel-lowering.ll
@@ -127,22 +127,18 @@
define float @lower_constantpool(float %a) nounwind {
; RV32I-SMALL-LABEL: lower_constantpool:
; RV32I-SMALL: # %bb.0:
-; RV32I-SMALL-NEXT: lui a1, %hi(.LCPI3_0)
-; RV32I-SMALL-NEXT: flw ft0, %lo(.LCPI3_0)(a1)
-; RV32I-SMALL-NEXT: fmv.w.x ft1, a0
-; RV32I-SMALL-NEXT: fadd.s ft0, ft1, ft0
-; RV32I-SMALL-NEXT: fmv.x.w a0, ft0
+; RV32I-SMALL-NEXT: lui a0, %hi(.LCPI3_0)
+; RV32I-SMALL-NEXT: flw ft0, %lo(.LCPI3_0)(a0)
+; RV32I-SMALL-NEXT: fadd.s fa0, fa0, ft0
; RV32I-SMALL-NEXT: ret
;
; RV32I-MEDIUM-LABEL: lower_constantpool:
; RV32I-MEDIUM: # %bb.0:
; RV32I-MEDIUM-NEXT: .LBB3_1: # Label of block must be emitted
-; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI3_0)
-; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB3_1)
-; RV32I-MEDIUM-NEXT: flw ft0, 0(a1)
-; RV32I-MEDIUM-NEXT: fmv.w.x ft1, a0
-; RV32I-MEDIUM-NEXT: fadd.s ft0, ft1, ft0
-; RV32I-MEDIUM-NEXT: fmv.x.w a0, ft0
+; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(.LCPI3_0)
+; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB3_1)
+; RV32I-MEDIUM-NEXT: flw ft0, 0(a0)
+; RV32I-MEDIUM-NEXT: fadd.s fa0, fa0, ft0
; RV32I-MEDIUM-NEXT: ret
%1 = fadd float %a, 1.0
ret float %1
Index: llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
===================================================================
--- llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
+++ llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64 %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64LP64F %s
Index: llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
===================================================================
--- llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
+++ llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32IF
; Exercises the ILP32 calling convention code in the case that f32 is a legal
Index: llvm/test/CodeGen/RISCV/calling-conv-half.ll
===================================================================
--- llvm/test/CodeGen/RISCV/calling-conv-half.ll
+++ llvm/test/CodeGen/RISCV/calling-conv-half.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF
-; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32F
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64F
; RUN: llc -mtriple=riscv32 -mattr=+f,+zfhmin -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32ZFHMIN
Index: llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
===================================================================
--- llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
+++ llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32
-; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=LP64
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32F
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -966,12 +966,16 @@
if (XLen == 32) {
if (hasExtension("d"))
return "ilp32d";
+ if (hasExtension("f"))
+ return "ilp32f";
if (hasExtension("e"))
return "ilp32e";
return "ilp32";
} else if (XLen == 64) {
if (hasExtension("d"))
return "lp64d";
+ if (hasExtension("f"))
+ return "lp64f";
return "lp64";
}
llvm_unreachable("Invalid XLEN");
Index: clang/test/Driver/riscv-cpus.c
===================================================================
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -62,14 +62,14 @@
// MCPU-SIFIVE-E24: "-nostdsysteminc" "-target-cpu" "sifive-e24"
// MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
// MCPU-SIFIVE-E24: "-target-feature" "+c"
-// MCPU-SIFIVE-E24: "-target-abi" "ilp32"
+// MCPU-SIFIVE-E24: "-target-abi" "ilp32f"
// mcpu with default march
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s
// MCPU-SIFIVE-E34: "-nostdsysteminc" "-target-cpu" "sifive-e34"
// MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
// MCPU-SIFIVE-E34: "-target-feature" "+c"
-// MCPU-SIFIVE-E34: "-target-abi" "ilp32"
+// MCPU-SIFIVE-E34: "-target-abi" "ilp32f"
// mcpu with mabi option
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s
@@ -118,7 +118,7 @@
// MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76"
// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
// MCPU-SIFIVE-E76: "-target-feature" "+c"
-// MCPU-SIFIVE-E76: "-target-abi" "ilp32"
+// MCPU-SIFIVE-E76: "-target-abi" "ilp32f"
// mcpu with mabi option
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s
Index: clang/test/Driver/riscv-abi.c
===================================================================
--- clang/test/Driver/riscv-abi.c
+++ clang/test/Driver/riscv-abi.c
@@ -4,8 +4,6 @@
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
-// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \
-// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \
@@ -24,6 +22,8 @@
// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s
+// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s
// CHECK-ILP32F: "-target-abi" "ilp32f"
@@ -51,8 +51,6 @@
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
-// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \
-// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \
@@ -62,6 +60,8 @@
// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64f -mabi=lp64f 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64F %s
+// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-LP64F %s
// CHECK-LP64F: "-target-abi" "lp64f"
Index: clang/test/CodeGen/RISCV/riscv-metadata.c
===================================================================
--- clang/test/CodeGen/RISCV/riscv-metadata.c
+++ clang/test/CodeGen/RISCV/riscv-metadata.c
@@ -1,9 +1,11 @@
// RUN: %clang_cc1 -triple riscv32 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-ILP32 %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -o - %s | FileCheck -check-prefix=EMPTY-ILP32F %s
// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -o - %s | FileCheck -check-prefix=EMPTY-ILP32D %s
// RUN: %clang_cc1 -triple riscv32 -target-abi ilp32 -emit-llvm -o - %s | FileCheck -check-prefix=ILP32 %s
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm -o - %s | FileCheck -check-prefix=ILP32F %s
// RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-feature +f -target-abi ilp32d -emit-llvm -o - %s | FileCheck -check-prefix=ILP32D %s
// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64F %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64D %s
// RUN: %clang_cc1 -triple riscv64 -target-abi lp64 -emit-llvm -o - %s | FileCheck -check-prefix=LP64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-abi lp64f -emit-llvm -o - %s | FileCheck -check-prefix=LP64F %s
@@ -16,12 +18,14 @@
// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - -target-cpu sifive-u74 %s | FileCheck -check-prefix=EMPTY-LP64 %s
// EMPTY-ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
+// EMPTY-ILP32F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32f"}
// EMPTY-ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
// ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
// ILP32F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32f"}
// ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
// EMPTY-LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
+// EMPTY-LP64F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64f"}
// EMPTY-LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}
// LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
// LP64F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64f"}
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