Author: Archibald Elliott Date: 2022-05-18T13:10:31+01:00 New Revision: 2321c36fbf763e273ed78b4209168ce783b5cf96
URL: https://github.com/llvm/llvm-project/commit/2321c36fbf763e273ed78b4209168ce783b5cf96 DIFF: https://github.com/llvm/llvm-project/commit/2321c36fbf763e273ed78b4209168ce783b5cf96.diff LOG: [ARM] Don't Enable AES Pass for Generic Cores This brings clang/llvm into line with GCC. The Pass is still enabled for the affected cores, but is now opt-in when using `-march=`. I also took the opportunity to add release notes for this change. Reviewed By: john.brawn Differential Revision: https://reviews.llvm.org/D125775 Added: Modified: clang/docs/ReleaseNotes.rst llvm/docs/ReleaseNotes.rst llvm/lib/Target/ARM/ARM.td Removed: ################################################################################ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 20920942c207..4fb4c662d71b 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -265,6 +265,11 @@ New Compiler Flags the parameter list were ``void``. There is no ``-fknr-functions`` or ``-fno-no-knr-functions`` flag; this feature cannot be disabled in language modes where it is required, such as C++ or C2x. +- A new ARM pass to workaround Cortex-A57 Erratum 1742098 and Cortex-A72 Erratum + 1655431 can be enabled using ``-mfix-cortex-a57-aes-1742098`` or + ``-mfix-cortex-a72-aes-1655431``. The pass is enabled when using either of + these cpus with ``-mcpu=`` and can be disabled using + ``-mno-fix-cortex-a57-aes-1742098`` or ``-mno-fix-cortex-a72-aes-1655431``. Deprecated Compiler Flags ------------------------- diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 54f2029aa25d..8529bb76e13e 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -99,6 +99,8 @@ Changes to the ARM Backend warnings will be generated and -mrestrict-it is now always off by default. Previously it was on by default for Armv8 and off for all other architecture versions. +* Added a pass to workaround Cortex-A57 Erratum 1742098 and Cortex-A72 + Erratum 1655431. This is enabled by default when targeting either CPU. Changes to the AVR Backend -------------------------- diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index de5dea1b2b2e..e8970b916a5f 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -1161,7 +1161,7 @@ include "ARMScheduleM7.td" // ARM processors // // Dummy CPU, used to target architectures -def : ProcessorModel<"generic", CortexA8Model, [FeatureFixCortexA57AES1742098]>; +def : ProcessorModel<"generic", CortexA8Model, []>; // FIXME: Several processors below are not using their own scheduler // model, but one of similar/previous processor. These should be fixed. _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
