Author: joker881 Date: 2022-04-14T12:29:15+08:00 New Revision: a4f47a99aafe57db0176ef7dad1a9ba72854439f
URL: https://github.com/llvm/llvm-project/commit/a4f47a99aafe57db0176ef7dad1a9ba72854439f DIFF: https://github.com/llvm/llvm-project/commit/a4f47a99aafe57db0176ef7dad1a9ba72854439f.diff LOG: RISCV] Add clang builtins for CLZ instruction. add intrinsic for CLZ Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D121915 Added: Modified: clang/include/clang/Basic/BuiltinsRISCV.def clang/lib/CodeGen/CGBuiltin.cpp clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def index 73ec6eae7e955..74b8c9ea6a949 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.def +++ b/clang/include/clang/Basic/BuiltinsRISCV.def @@ -18,6 +18,8 @@ // Zbb extension TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb") TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit") +TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb") +TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit") // Zbc or Zbkc extension TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc") diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 4ad4acc0be6b1..3adabcbf4bc97 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -18992,6 +18992,8 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, default: llvm_unreachable("unexpected builtin ID"); case RISCV::BI__builtin_riscv_orc_b_32: case RISCV::BI__builtin_riscv_orc_b_64: + case RISCV::BI__builtin_riscv_clz_32: + case RISCV::BI__builtin_riscv_clz_64: case RISCV::BI__builtin_riscv_clmul: case RISCV::BI__builtin_riscv_clmulh: case RISCV::BI__builtin_riscv_clmulr: @@ -19037,6 +19039,11 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_orc_b_64: ID = Intrinsic::riscv_orc_b; break; + case RISCV::BI__builtin_riscv_clz_32: + case RISCV::BI__builtin_riscv_clz_64: { + Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType()); + return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)}); + } // Zbc case RISCV::BI__builtin_riscv_clmul: diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c index 1eb0250893f25..c1827b1edbf5b 100644 --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c @@ -13,3 +13,15 @@ int orc_b_32(int a) { return __builtin_riscv_orc_b_32(a); } + +// RV32ZBB-LABEL: @clz_32( +// RV32ZBB-NEXT: entry: +// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV32ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false) +// RV32ZBB-NEXT: ret i32 [[TMP1]] +// +int clz_32(int a) { + return __builtin_riscv_clz_32(a); +} \ No newline at end of file diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c index 013096743078c..da2930c891201 100644 --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c @@ -25,3 +25,27 @@ int orc_b_32(int a) { long orc_b_64(long a) { return __builtin_riscv_orc_b_64(a); } + +// RV64ZBB-LABEL: @clz_32( +// RV64ZBB-NEXT: entry: +// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV64ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false) +// RV64ZBB-NEXT: ret i32 [[TMP1]] +// +int clz_32(int a) { + return __builtin_riscv_clz_32(a); +} + +// RV64ZBB-LABEL: @clz_64( +// RV64ZBB-NEXT: entry: +// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBB-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false) +// RV64ZBB-NEXT: ret i64 [[TMP1]] +// +long clz_64(long a) { + return __builtin_riscv_clz_64(a); +} \ No newline at end of file _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
