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Add zihintntl compressed instructions and some files related to zihintntl
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D121779
Files:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rv32zihintntl-invalid.s
llvm/test/MC/RISCV/rv32zihintntl-valid.s
llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
llvm/test/MC/RISCV/rv32zihintntlc-valid.s
Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: ntl.p1
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-OBJ: ntl.pall
+# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
+ntl.pall
+
+# CHECK-ASM-AND-OBJ: ntl.s1
+# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00]
+ntl.s1
+
+# CHECK-ASM-AND-OBJ: ntl.all
+# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00]
+ntl.all
+
+# CHECK-ASM-AND-OBJ: c.ntl.p1
+# CHECK-ASM: encoding: [0x0a,0x90]
+c.ntl.p1
+
+# CHECK-ASM-AND-OBJ: c.ntl.pall
+# CHECK-ASM: encoding: [0x0e,0x90]
+c.ntl.pall
+
+# CHECK-ASM-AND-OBJ: c.ntl.s1
+# CHECK-ASM: encoding: [0x12,0x90]
+c.ntl.s1
+
+# CHECK-ASM-AND-OBJ: c.ntl.all
+# CHECK-ASM: encoding: [0x16,0x90]
+c.ntl.all
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+
+c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+c.ntl.s1 3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.all 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+
+c.ntl.p1 t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.pall t0, t1 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+c.ntl.s1 t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.all t0, t1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+
Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: add zero, zero, sp
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, gp
+# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
+ntl.pall
+
+# CHECK-ASM-AND-OBJ: add zero, zero, tp
+# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00]
+ntl.s1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, t0
+# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00]
+ntl.all
Index: llvm/test/MC/RISCV/rv32zihintntl-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntl-invalid.s
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl < %s 2>&1 | FileCheck %s
+
+ntl.p1 1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.pall 2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+ntl.s1 3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.all 4 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+ntl.p1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.pall t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+ntl.s1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.all t0, t1 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -175,3 +175,9 @@
.attribute arch, "rv32i_zk1p0"
# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+
+.attribute arch, "rv32izihintntl0p2"
+# CHECK: attribute 5, "rv32i2p0_zihintntl0p2"
+
+.attribute arch, "rv32iczihintntl0p2"
+# CHECK: attribute 5, "rv32i2p0_c2p0_zihintntl0p2"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===================================================================
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -6,6 +6,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
; RUN: llc -mtriple=riscv32 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV32ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV32ZIHINTNTL %s
; RUN: llc -mtriple=riscv32 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV32ZFHMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
@@ -42,6 +43,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
; RUN: llc -mtriple=riscv64 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV64ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV64ZIHINTNTL %s
; RUN: llc -mtriple=riscv64 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV64ZFHMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
@@ -79,6 +81,7 @@
; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
; RV32C: .attribute 5, "rv32i2p0_c2p0"
; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p0_zihintpause2p0"
+; RV32ZIHINTNTL: .attribute 5, "rv32i2p0_zihintntl0p2"
; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0"
; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
@@ -116,6 +119,7 @@
; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
; RV64C: .attribute 5, "rv64i2p0_c2p0"
; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p0_zihintpause2p0"
+; RV64ZIHINTNTL: .attribute 5, "rv64i2p0_zihintntl0p2"
; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0"
; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0"
; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -66,6 +66,7 @@
bool HasStdExtD = false;
bool HasStdExtC = false;
bool HasStdExtZihintpause = false;
+ bool HasStdExtZihintntl = false;
bool HasStdExtZba = false;
bool HasStdExtZbb = false;
bool HasStdExtZbc = false;
@@ -163,6 +164,7 @@
bool hasStdExtC() const { return HasStdExtC; }
bool hasStdExtV() const { return HasStdExtV; }
bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
+ bool hasStdExtZihintntl() const { return HasStdExtZihintntl; }
bool hasStdExtZba() const { return HasStdExtZba; }
bool hasStdExtZbb() const { return HasStdExtZbb; }
bool hasStdExtZbc() const { return HasStdExtZbc; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfoC.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -695,6 +695,13 @@
// Assembler Pseudo Instructions
//===----------------------------------------------------------------------===//
+let Predicates = [HasStdExtC, HasRVCHints, HasStdExtZihintntl] in {
+def : InstAlias<"c.ntl.p1", (C_ADD_HINT X0, X2)>;
+def : InstAlias<"c.ntl.pall", (C_ADD_HINT X0, X3)>;
+def : InstAlias<"c.ntl.s1", (C_ADD_HINT X0, X4)>;
+def : InstAlias<"c.ntl.all", (C_ADD_HINT X0, X5)>;
+} // Predicates = [HasStdExtC, HasRVCHints, HasStdExtZihintntl]
+
let EmitPriority = 0 in {
let Predicates = [HasStdExtC, HasStdExtD] in
def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRC:$rs1, 0)>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -915,6 +915,13 @@
def : InstAlias<"hfence.vvma", (HFENCE_VVMA X0, X0)>;
def : InstAlias<"hfence.vvma $rs", (HFENCE_VVMA GPR:$rs, X0)>;
+let Predicates = [HasStdExtZihintntl] in {
+ def : InstAlias<"ntl.p1", (ADD X0, X0, X2)>;
+ def : InstAlias<"ntl.pall", (ADD X0, X0, X3)>;
+ def : InstAlias<"ntl.s1", (ADD X0, X0, X4)>;
+ def : InstAlias<"ntl.all", (ADD X0, X0, X5)>;
+} // Predicates = [HasStdExtZihintntl]
+
let EmitPriority = 0 in {
def : InstAlias<"lb $rd, (${rs1})",
(LB GPR:$rd, GPR:$rs1, 0)>;
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -48,6 +48,13 @@
AssemblerPredicate<(all_of FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
+def FeatureStdExtZihintntl
+ : SubtargetFeature<"experimental-zihintntl", "HasStdExtZihintntl", "true",
+ "'zihintntl' (Non-Temporal Locality Hints)">;
+def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
+ AssemblerPredicate<(all_of FeatureStdExtZihintntl),
+ "'Zihintntl' (Non-Temporal Locality Hints)">;
+
def FeatureStdExtZfhmin
: SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -98,6 +98,8 @@
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
+ {"zihintntl", RISCVExtensionVersion{0, 2}},
+
{"zbe", RISCVExtensionVersion{0, 93}},
{"zbf", RISCVExtensionVersion{0, 93}},
{"zbm", RISCVExtensionVersion{0, 93}},
Index: clang/test/Preprocessor/riscv-target-features.c
===================================================================
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -18,6 +18,7 @@
// CHECK-NOT: __riscv_compressed
// CHECK-NOT: __riscv_b
// CHECK-NOT: __riscv_bitmanip
+// CHECK-NOT: __riscv_zihintntl
// CHECK-NOT: __riscv_zba
// CHECK-NOT: __riscv_zbb
// CHECK-NOT: __riscv_zbc
@@ -108,6 +109,14 @@
// CHECK-C-EXT: __riscv_c 2000000{{$}}
// CHECK-C-EXT: __riscv_compressed 1
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izihintntl0p2 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izihintntl0p2 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
+// CHECK-ZIHINTNTL-EXT: __riscv_zihintntl 2000{{$}}
+
// RUN: %clang -target riscv32-unknown-linux-gnu \
// RUN: -march=rv32izba1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
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