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In D70401#3250049 <https://reviews.llvm.org/D70401#3250049>, @khchen wrote:

> 1. please add a check here 
> <https://github.com/llvm/llvm-project/blob/c29d6c410e769938ed5db1090a1b894cf6061a4e/llvm/lib/Support/RISCVISAInfo.cpp#L704>
>  and a clang cc1 test for it.
> 2. Have you try to run llvm-test-suite with rv32e config on qemu?



1. Thanks, I may do it later. And here is a question: the comment 
<https://github.com/llvm/llvm-project/blob/c29d6c410e769938ed5db1090a1b894cf6061a4e/llvm/lib/Support/RISCVISAInfo.cpp#L704>
 says `It is illegal to specify 'e' extensions with 'f' and 'd'`.

While ilp32e 
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#ilp32e-calling-convention>
 says:

> The ILP32E calling convention is not compatible with ISAs that have registers 
> that require load and store alignments of more than 32 bits. In particular, 
> this calling convention must not be used with the D ISA extension.

And, the RV32E 
<https://github.com/riscv/riscv-isa-manual/blob/master/src/rv32e.tex> chapter 
in RISCV ISA manual says:

> RV32E can be combined with all current standard extensions.

If I understand correctly, E can't be combined with D in current specification 
since E must use ILP32E calling convention.

2. I have run llvm-test-suite with rv32e on qemu, and found no major fault for 
current implementation. Some tests are disabled because they can't run on bare 
mental (sees Disabled llvm-test-suite cases <https://pastebin.com/9j4ydQFf>).

There are some failed tests due to floating-point precision, but I saw the same 
result when run with  rv32gc on bare mental. I haven't taken the time to find 
out the reason, but I guess it may be soft-float issues.


Repository:
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  https://reviews.llvm.org/D70401/new/

https://reviews.llvm.org/D70401

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