craig.topper added a comment. In D93298#3355088 <https://reviews.llvm.org/D93298#3355088>, @craig.topper wrote:
> In D93298#3354313 <https://reviews.llvm.org/D93298#3354313>, @krasimir wrote: > >> @achieveartificialintelligence thank you for looking into this, sorry for >> the late reply! >> >> It looks like the latest version addresses @nikic's IR reproducer with >> `-mtriple=riscv32`. >> >> There seems to be an error trying this out with `-mtriple=riscv64`: >> >> % cat test.ll >> define float @test(float %x) { >> %1 = tail call float asm sideeffect alignstack "mv a0, a0", >> "={x10},{x10}"(float 0.000000e+00) >> ret float 0.000000e+00 >> } >> % llc -mtriple=riscv32 -mattr=+d test.ll >> % llc -mtriple=riscv64 -mattr=+d test.ll >> error: couldn't allocate output register for constraint '{x10}' >> >> I'm not sure if this is intended to work `-mtriple=riscv64`, but judging by >> the newly added test `RUN: llc -mtriple=riscv64 ...` line it seems like it >> should? > > My patch was only partially correct. I'll fix it I just pushed 6cb42cd6669785f3b611106e1b6b38bbe65733a9 <https://reviews.llvm.org/rG6cb42cd6669785f3b611106e1b6b38bbe65733a9> to hopefully fix this. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
