achieveartificialintelligence marked an inline comment as done. achieveartificialintelligence added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:557 + +let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in +def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add ---------------- Jim wrote: > Is register pair only on RV32 for used as f64? Yes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
