Jimerlife updated this revision to Diff 402414.
Jimerlife retitled this revision from "[RISCV][NFC] Add "zbkc" predicate for
clmul and clmulh pattern" to "[RISCV] Adjust predicates and update intrinsic
for clmul and clmulh in Zbkc extension ".
Jimerlife edited the summary of this revision.
Jimerlife added a reviewer: kito-cheng.
Jimerlife added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
1. Add IR tests for clmul and clmulh in zbkc extension.
2. Updating BuiltinsRISCV.def, I rename "__builtin__riscv__clmul" to
"__builtin_riscv_clmul_kc" in zbkc extension, because cannot share same name
"__builtin__riscv_clmul" in zbc and zbkc extension.
3. Add C tests for clmul and clmulh in zbkc extension
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D118011/new/
https://reviews.llvm.org/D118011
Files:
clang/include/clang/Basic/BuiltinsRISCV.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
Index: llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zbc -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64ZBC
+; RUN: llc -mtriple=riscv64 -mattr=+zbkc -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64ZBKC
+
+declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+
+define i64 @clmul64(i64 %a, i64 %b) nounwind {
+; RV64ZBC-LABEL: clmul64:
+; RV64ZBC: # %bb.0:
+; RV64ZBC-NEXT: clmul a0, a0, a1
+; RV64ZBC-NEXT: ret
+;
+; RV64ZBKC-LABEL: clmul64:
+; RV64ZBKC: # %bb.0:
+; RV64ZBKC-NEXT: clmul a0, a0, a1
+; RV64ZBKC-NEXT: ret
+ %tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
+
+define i64 @clmul64h(i64 %a, i64 %b) nounwind {
+; RV64ZBC-LABEL: clmul64h:
+; RV64ZBC: # %bb.0:
+; RV64ZBC-NEXT: clmulh a0, a0, a1
+; RV64ZBC-NEXT: ret
+;
+; RV64ZBKC-LABEL: clmul64h:
+; RV64ZBKC: # %bb.0:
+; RV64ZBKC-NEXT: clmulh a0, a0, a1
+; RV64ZBKC-NEXT: ret
+ %tmp = call i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zbc -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32ZBC
+; RUN: llc -mtriple=riscv32 -mattr=+zbkc -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32ZBKC
+
+declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+
+define i32 @clmul32(i32 %a, i32 %b) nounwind {
+; RV32ZBC-LABEL: clmul32:
+; RV32ZBC: # %bb.0:
+; RV32ZBC-NEXT: clmul a0, a0, a1
+; RV32ZBC-NEXT: ret
+;
+; RV32ZBKC-LABEL: clmul32:
+; RV32ZBKC: # %bb.0:
+; RV32ZBKC-NEXT: clmul a0, a0, a1
+; RV32ZBKC-NEXT: ret
+ %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+
+define i32 @clmul32h(i32 %a, i32 %b) nounwind {
+; RV32ZBC-LABEL: clmul32h:
+; RV32ZBC: # %bb.0:
+; RV32ZBC-NEXT: clmulh a0, a0, a1
+; RV32ZBC-NEXT: ret
+;
+; RV32ZBKC-LABEL: clmul32h:
+; RV32ZBKC: # %bb.0:
+; RV32ZBKC-NEXT: clmulh a0, a0, a1
+; RV32ZBKC-NEXT: ret
+ %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -1131,11 +1131,13 @@
(PACKUW GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbp, IsRV64]
-let Predicates = [HasStdExtZbc] in {
+let Predicates = [HasStdExtZbcOrZbkc] in {
def : PatGprGpr<int_riscv_clmul, CLMUL>;
def : PatGprGpr<int_riscv_clmulh, CLMULH>;
+} // Predicates = [HasStdExtZbcOrZbkc]
+
+let Predicates = [HasStdExtZbc] in
def : PatGprGpr<int_riscv_clmulr, CLMULR>;
-} // Predicates = [HasStdExtZbc]
let Predicates = [HasStdExtZbe] in {
def : PatGprGpr<riscv_bcompress, BCOMPRESS>;
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -88,9 +88,11 @@
// Zbb
def int_riscv_orc_b : BitManipGPRIntrinsics;
- // Zbc
+ // ZbcorZbkc
def int_riscv_clmul : BitManipGPRGPRIntrinsics;
def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
+
+ // Zbc
def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
// Zbe
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkc -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZBKC
+
+// RV64ZBKC-LABEL: @clmul(
+// RV64ZBKC-NEXT: entry:
+// RV64ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBKC-NEXT: ret i64 [[TMP2]]
+//
+long clmul(long a, long b) {
+ return __builtin_riscv_clmul_kc(a, b);
+}
+
+// RV64ZBKC-LABEL: @clmulh(
+// RV64ZBKC-NEXT: entry:
+// RV64ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBKC-NEXT: ret i64 [[TMP2]]
+//
+long clmulh(long a, long b) {
+ return __builtin_riscv_clmulh_kc(a, b);
+}
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkc -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZBKC
+
+// RV32ZBKC-LABEL: @clmul(
+// RV32ZBKC-NEXT: entry:
+// RV32ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBKC-NEXT: ret i32 [[TMP2]]
+//
+long clmul(long a, long b) {
+ return __builtin_riscv_clmul_kc(a, b);
+}
+
+// RV32ZBKC-LABEL: @clmulh(
+// RV32ZBKC-NEXT: entry:
+// RV32ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBKC-NEXT: ret i32 [[TMP2]]
+//
+long clmulh(long a, long b) {
+ return __builtin_riscv_clmulh_kc(a, b);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -18827,6 +18827,8 @@
case RISCV::BI__builtin_riscv_orc_b_64:
case RISCV::BI__builtin_riscv_clmul:
case RISCV::BI__builtin_riscv_clmulh:
+ case RISCV::BI__builtin_riscv_clmul_kc:
+ case RISCV::BI__builtin_riscv_clmulh_kc:
case RISCV::BI__builtin_riscv_clmulr:
case RISCV::BI__builtin_riscv_bcompress_32:
case RISCV::BI__builtin_riscv_bcompress_64:
@@ -18866,13 +18868,17 @@
ID = Intrinsic::riscv_orc_b;
break;
- // Zbc
+ // ZbcOrZbkc
case RISCV::BI__builtin_riscv_clmul:
+ case RISCV::BI__builtin_riscv_clmul_kc:
ID = Intrinsic::riscv_clmul;
break;
case RISCV::BI__builtin_riscv_clmulh:
+ case RISCV::BI__builtin_riscv_clmulh_kc:
ID = Intrinsic::riscv_clmulh;
break;
+
+ // Zbc
case RISCV::BI__builtin_riscv_clmulr:
ID = Intrinsic::riscv_clmulr;
break;
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===================================================================
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -24,6 +24,10 @@
TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc")
TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "zbc")
+// Zbkc extension
+TARGET_BUILTIN(__builtin_riscv_clmul_kc, "LiLiLi", "nc", "zbkc")
+TARGET_BUILTIN(__builtin_riscv_clmulh_kc, "LiLiLi", "nc", "zbkc")
+
// Zbe extension
TARGET_BUILTIN(__builtin_riscv_bcompress_32, "ZiZiZi", "nc", "experimental-zbe")
TARGET_BUILTIN(__builtin_riscv_bcompress_64, "WiWiWi", "nc",
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