craig.topper added inline comments.
================ Comment at: clang/test/Preprocessor/riscv-target-features.c:207 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv32izfhmin1p0 -x c -E -dM %s \ ---------------- If it's not experimental now, do you need -menable-experimental-extensions? ================ Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td:1 //===-- RISCVInstrInfoFH.td - RISC-V 'FH' instructions -----*- tablegen -*-===// // ---------------- While you're in here can you fix this line by replacing 'FH' with 'Zfh' Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117098/new/ https://reviews.llvm.org/D117098 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
