yaxunl added a comment. In D109496#3103963 <https://reviews.llvm.org/D109496#3103963>, @mizvekov wrote:
> Thanks for reporting this! > > This change in the standard was worked a long time ago, and there was some > expectation that there would be follow up work to add new partial ordering > rules so that reasonable code would keep working. But the person behind that > effort stopped participating in the process, so this fell into the cracks. > > We tried with this patch here to see if the rules would just work out as > intended. Another option, which I believe is what GCC does, is to not do the > DR part and apply it only to c++17 and later. > However the breakage example you posted seems to be from a CUDA library which > is not usable in the GCC ecosystem, is that correct? And that this library > might be modern and used with newer standard as well? > > If that is the case, the GCC solution might not be good for us anyway, and > the simplest thing would be to just implement some new rules. The regression happens with rocThrust, which is CUDA Thrust ported to HIP language. However, I think the same issue would happen to CUDA Thrust. These libraries need to work with C++17, therefore it is better to implement some new rules. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109496/new/ https://reviews.llvm.org/D109496 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
