NeHuang updated this revision to Diff 383506.
NeHuang added a comment.
Addressed review comments from @nemanjai and @amyk
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D112285/new/
https://reviews.llvm.org/D112285
Files:
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -1,19 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
; tw
declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
define dso_local void @test__twlgt(i32 %a, i32 %b) {
; CHECK-LABEL: test__twlgt:
; CHECK: # %bb.0:
-; CHECK-NEXT: twlgt 3, 4
+; CHECK-NEXT: twlgt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
ret void
@@ -22,7 +22,7 @@
define dso_local void @test__twllt(i32 %a, i32 %b) {
; CHECK-LABEL: test__twllt:
; CHECK: # %bb.0:
-; CHECK-NEXT: twllt 3, 4
+; CHECK-NEXT: twllt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
ret void
@@ -31,7 +31,7 @@
define dso_local void @test__tw3(i32 %a, i32 %b) {
; CHECK-LABEL: test__tw3:
; CHECK: # %bb.0:
-; CHECK-NEXT: tw 3, 3, 4
+; CHECK-NEXT: tw 3, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
ret void
@@ -40,7 +40,7 @@
define dso_local void @test__tweq(i32 %a, i32 %b) {
; CHECK-LABEL: test__tweq:
; CHECK: # %bb.0:
-; CHECK-NEXT: tweq 3, 4
+; CHECK-NEXT: tweq r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
ret void
@@ -49,7 +49,7 @@
define dso_local void @test__twlge(i32 %a, i32 %b) {
; CHECK-LABEL: test__twlge:
; CHECK: # %bb.0:
-; CHECK-NEXT: tw 5, 3, 4
+; CHECK-NEXT: tw 5, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
ret void
@@ -58,7 +58,7 @@
define dso_local void @test__twlle(i32 %a, i32 %b) {
; CHECK-LABEL: test__twlle:
; CHECK: # %bb.0:
-; CHECK-NEXT: tw 6, 3, 4
+; CHECK-NEXT: tw 6, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
ret void
@@ -67,7 +67,7 @@
define dso_local void @test__twgt(i32 %a, i32 %b) {
; CHECK-LABEL: test__twgt:
; CHECK: # %bb.0:
-; CHECK-NEXT: twgt 3, 4
+; CHECK-NEXT: twgt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
ret void
@@ -76,7 +76,7 @@
define dso_local void @test__twge(i32 %a, i32 %b) {
; CHECK-LABEL: test__twge:
; CHECK: # %bb.0:
-; CHECK-NEXT: tw 12, 3, 4
+; CHECK-NEXT: tw 12, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
ret void
@@ -85,7 +85,7 @@
define dso_local void @test__twlt(i32 %a, i32 %b) {
; CHECK-LABEL: test__twlt:
; CHECK: # %bb.0:
-; CHECK-NEXT: twlt 3, 4
+; CHECK-NEXT: twlt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
ret void
@@ -94,7 +94,7 @@
define dso_local void @test__twle(i32 %a, i32 %b) {
; CHECK-LABEL: test__twle:
; CHECK: # %bb.0:
-; CHECK-NEXT: tw 20, 3, 4
+; CHECK-NEXT: tw 20, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
ret void
@@ -103,7 +103,7 @@
define dso_local void @test__twne24(i32 %a, i32 %b) {
; CHECK-LABEL: test__twne24:
; CHECK: # %bb.0:
-; CHECK-NEXT: twne 3, 4
+; CHECK-NEXT: twne r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
ret void
@@ -112,7 +112,7 @@
define dso_local void @test__twu(i32 %a, i32 %b) {
; CHECK-LABEL: test__twu:
; CHECK: # %bb.0:
-; CHECK-NEXT: twu 3, 4
+; CHECK-NEXT: twu r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
ret void
@@ -121,18 +121,225 @@
define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
; CHECK-LABEL: test__tw_no_match:
; CHECK: # %bb.0:
-; CHECK-NEXT: tw 13, 3, 4
+; CHECK-NEXT: tw 13, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
ret void
}
+; tw -> twi
+define dso_local void @test__twi_boundary_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twi_boundary_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twi 3, r3, 32767
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 32767, i32 3)
+ ret void
+}
+
+define dso_local void @test__twi_boundary_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twi_boundary_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twi 3, r3, 32767
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 32767, i32 %a, i32 3)
+ ret void
+}
+
+define dso_local void @test__twi_boundary1_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twi_boundary1_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twi 3, r3, -32768
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 -32768, i32 3)
+ ret void
+}
+
+define dso_local void @test__twi_boundary1_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twi_boundary1_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twi 3, r3, -32768
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 -32768, i32 %a, i32 3)
+ ret void
+}
+
+define dso_local void @test__tw_boundary2_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tw_boundary2_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lis r4, 0
+; CHECK-NEXT: ori r4, r4, 32768
+; CHECK-NEXT: tw 3, r3, r4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 32768, i32 3)
+ ret void
+}
+
+define dso_local void @test__tw_boundary2_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tw_boundary2_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lis r4, 0
+; CHECK-NEXT: ori r4, r4, 32768
+; CHECK-NEXT: tw 3, r4, r3
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 32768, i32 %a, i32 3)
+ ret void
+}
+
+define dso_local void @test__tw_boundary3_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tw_boundary3_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lis r4, -1
+; CHECK-NEXT: ori r4, r4, 32767
+; CHECK-NEXT: tw 3, r3, r4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 -32769, i32 3)
+ ret void
+}
+
+define dso_local void @test__tw_boundary3_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tw_boundary3_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lis r4, -1
+; CHECK-NEXT: ori r4, r4, 32767
+; CHECK-NEXT: tw 3, r4, r3
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 -32769, i32 %a, i32 3)
+ ret void
+}
+
+define dso_local void @test__twlgti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twlgti_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twlgti r3, 0
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 0, i32 1)
+ ret void
+}
+
+define dso_local void @test__twllti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twllti_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twllti r3, 0
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 0, i32 %a, i32 1)
+ ret void
+}
+
+define dso_local void @test__twllti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twllti_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twllti r3, 1
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 1, i32 2)
+ ret void
+}
+
+define dso_local void @test__twlgti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twlgti_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twlgti r3, 1
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 1, i32 %a, i32 2)
+ ret void
+}
+
+define dso_local void @test__tweqi_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tweqi_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tweqi r3, 2
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 2, i32 4)
+ ret void
+}
+
+define dso_local void @test__tweqi_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tweqi_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tweqi r3, 2
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 2, i32 %a, i32 4)
+ ret void
+}
+
+define dso_local void @test__twgti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twgti_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twgti r3, 16
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 16, i32 8)
+ ret void
+}
+
+define dso_local void @test__twlti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twlti_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twlti r3, 16
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 16, i32 %a, i32 8)
+ ret void
+}
+
+define dso_local void @test__twlti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twlti_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twlti r3, 64
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 64, i32 16)
+ ret void
+}
+
+define dso_local void @test__twgti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twgti_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twgti r3, 64
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 64, i32 %a, i32 16)
+ ret void
+}
+
+define dso_local void @test__twnei_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twnei_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twnei r3, 256
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 256, i32 24)
+ ret void
+}
+
+define dso_local void @test__twnei_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twnei_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twnei r3, 256
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 256, i32 %a, i32 24)
+ ret void
+}
+
+define dso_local void @test__twui_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twui_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twui r3, 512
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 512, i32 31)
+ ret void
+}
+
+define dso_local void @test__twui_imm_imm(i32 %a) {
+; CHECK-LABEL: test__twui_imm_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twui r3, 512
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 512, i32 %a, i32 31)
+ ret void
+}
+
; trap
declare void @llvm.ppc.trap(i32 %a)
define dso_local void @test__trap(i32 %a) {
; CHECK-LABEL: test__trap:
; CHECK: # %bb.0:
-; CHECK-NEXT: twnei 3, 0
+; CHECK-NEXT: twnei r3, 0
; CHECK-NEXT: blr
call void @llvm.ppc.trap(i32 %a)
ret void
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
@@ -1,17 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
; tdw
declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg)
define dso_local void @test__tdwlgt(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwlgt:
; CHECK: # %bb.0:
-; CHECK-NEXT: tdlgt 3, 4
+; CHECK-NEXT: tdlgt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1)
ret void
@@ -20,7 +20,7 @@
define dso_local void @test__tdwllt(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwllt:
; CHECK: # %bb.0:
-; CHECK-NEXT: tdllt 3, 4
+; CHECK-NEXT: tdllt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 2)
ret void
@@ -29,7 +29,7 @@
define dso_local void @test__tdw3(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdw3:
; CHECK: # %bb.0:
-; CHECK-NEXT: td 3, 3, 4
+; CHECK-NEXT: td 3, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 3)
ret void
@@ -37,7 +37,7 @@
define dso_local void @test__tdweq(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdweq:
; CHECK: # %bb.0:
-; CHECK-NEXT: tdeq 3, 4
+; CHECK-NEXT: tdeq r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 4)
ret void
@@ -46,7 +46,7 @@
define dso_local void @test__tdwlge(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwlge:
; CHECK: # %bb.0:
-; CHECK-NEXT: td 5, 3, 4
+; CHECK-NEXT: td 5, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 5)
ret void
@@ -55,7 +55,7 @@
define dso_local void @test__tdwlle(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwlle:
; CHECK: # %bb.0:
-; CHECK-NEXT: td 6, 3, 4
+; CHECK-NEXT: td 6, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 6)
ret void
@@ -64,7 +64,7 @@
define dso_local void @test__tdwgt(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwgt:
; CHECK: # %bb.0:
-; CHECK-NEXT: tdgt 3, 4
+; CHECK-NEXT: tdgt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 8)
ret void
@@ -73,7 +73,7 @@
define dso_local void @test__tdwge(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwge:
; CHECK: # %bb.0:
-; CHECK-NEXT: td 12, 3, 4
+; CHECK-NEXT: td 12, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 12)
ret void
@@ -82,7 +82,7 @@
define dso_local void @test__tdwlt(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwlt:
; CHECK: # %bb.0:
-; CHECK-NEXT: tdlt 3, 4
+; CHECK-NEXT: tdlt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 16)
ret void
@@ -91,7 +91,7 @@
define dso_local void @test__tdwle(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwle:
; CHECK: # %bb.0:
-; CHECK-NEXT: td 20, 3, 4
+; CHECK-NEXT: td 20, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 20)
ret void
@@ -100,7 +100,7 @@
define dso_local void @test__tdwne24(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwne24:
; CHECK: # %bb.0:
-; CHECK-NEXT: tdne 3, 4
+; CHECK-NEXT: tdne r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 24)
ret void
@@ -109,7 +109,7 @@
define dso_local void @test__tdw31(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdw31:
; CHECK: # %bb.0:
-; CHECK-NEXT: tdu 3, 4
+; CHECK-NEXT: tdu r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 31)
ret void
@@ -118,18 +118,225 @@
define dso_local void @test__tdw_no_match(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdw_no_match:
; CHECK: # %bb.0:
-; CHECK-NEXT: td 13, 3, 4
+; CHECK-NEXT: td 13, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 13)
ret void
}
+; tdw -> tdi
+define dso_local void @test__tdi_reg_imm_boundary(i64 %a) {
+; CHECK-LABEL: test__tdi_reg_imm_boundary:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdi 3, r3, 32767
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 32767, i32 3)
+ ret void
+}
+
+define dso_local void @test__tdi_imm_reg_boundary(i64 %a) {
+; CHECK-LABEL: test__tdi_imm_reg_boundary:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdi 3, r3, 32767
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 32767, i64 %a, i32 3)
+ ret void
+}
+
+define dso_local void @test__tdi_reg_imm_boundary1(i64 %a) {
+; CHECK-LABEL: test__tdi_reg_imm_boundary1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdi 3, r3, -32768
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 -32768, i32 3)
+ ret void
+}
+
+define dso_local void @test__tdi_imm_reg_boundary1(i64 %a) {
+; CHECK-LABEL: test__tdi_imm_reg_boundary1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdi 3, r3, -32768
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 -32768, i64 %a, i32 3)
+ ret void
+}
+
+define dso_local void @test__td_reg_imm_boundary2(i64 %a) {
+; CHECK-LABEL: test__td_reg_imm_boundary2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li r4, 0
+; CHECK-NEXT: ori r4, r4, 32768
+; CHECK-NEXT: td 3, r4, r3
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 32768, i64 %a, i32 3)
+ ret void
+}
+
+define dso_local void @test__td_imm_reg_boundary2(i64 %a) {
+; CHECK-LABEL: test__td_imm_reg_boundary2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li r4, 0
+; CHECK-NEXT: ori r4, r4, 32768
+; CHECK-NEXT: td 3, r3, r4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 32768, i32 3)
+ ret void
+}
+
+define dso_local void @test__td_reg_imm_boundary3(i64 %a) {
+; CHECK-LABEL: test__td_reg_imm_boundary3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lis r4, -1
+; CHECK-NEXT: ori r4, r4, 32767
+; CHECK-NEXT: td 3, r3, r4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 -32769, i32 3)
+ ret void
+}
+
+define dso_local void @test__td_imm_reg_boundary3(i64 %a) {
+; CHECK-LABEL: test__td_imm_reg_boundary3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lis r4, -1
+; CHECK-NEXT: ori r4, r4, 32767
+; CHECK-NEXT: td 3, r3, r4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 -32769, i32 3)
+ ret void
+}
+
+define dso_local void @test__tdlgti_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdlgti_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdlgti r3, 0
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 0, i32 1)
+ ret void
+}
+
+define dso_local void @test__tdllti_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdllti_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdllti r3, 0
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 0, i64 %a, i32 1)
+ ret void
+}
+
+define dso_local void @test__tdllti_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdllti_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdllti r3, 1
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 1, i32 2)
+ ret void
+}
+
+define dso_local void @test__tdlgti_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdlgti_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdlgti r3, 1
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 1, i64 %a, i32 2)
+ ret void
+}
+
+define dso_local void @test__tdeqi_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdeqi_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdeqi r3, 2
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 2, i32 4)
+ ret void
+}
+
+define dso_local void @test__tdeqi_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdeqi_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdeqi r3, 2
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 2, i64 %a, i32 4)
+ ret void
+}
+
+define dso_local void @test__tdgti_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdgti_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdgti r3, 16
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 16, i32 8)
+ ret void
+}
+
+define dso_local void @test__tdlti_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdlti_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdlti r3, 16
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 16, i64 %a, i32 8)
+ ret void
+}
+
+define dso_local void @test__tdlti_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdlti_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdlti r3, 64
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 64, i32 16)
+ ret void
+}
+
+define dso_local void @test__tdgti_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdgti_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdgti r3, 64
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 64, i64 %a, i32 16)
+ ret void
+}
+
+define dso_local void @test__tdnei_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdnei_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdnei r3, 256
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 256, i32 24)
+ ret void
+}
+
+define dso_local void @test__tdnei_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdnei_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdnei r3, 256
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 256, i64 %a, i32 24)
+ ret void
+}
+
+define dso_local void @test__tdui_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdui_reg_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdui r3, 512
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 512, i32 31)
+ ret void
+}
+
+define dso_local void @test__tdui_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdui_imm_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdui r3, 512
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 512, i64 %a, i32 31)
+ ret void
+}
+
; trapd
declare void @llvm.ppc.trapd(i64 %a)
define dso_local void @test__trapd(i64 %a) {
; CHECK-LABEL: test__trapd:
; CHECK: # %bb.0:
-; CHECK-NEXT: tdnei 3, 0
+; CHECK-NEXT: tdnei r3, 0
; CHECK-NEXT: blr
call void @llvm.ppc.trapd(i64 %a)
ret void
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5477,8 +5477,6 @@
(STWCX gprc:$A, ForceXForm:$dst)>;
def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A),
(STBCX gprc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM),
- (TW $IMM, $A, $B)>;
def : Pat<(int_ppc_trap gprc:$A),
(TWI 24, $A, 0)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1877,8 +1877,6 @@
def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
(STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
- (TD $IMM, $A, $B)>;
// trapd
def : Pat<(int_ppc_trapd g8rc:$A),
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -4997,6 +4997,61 @@
}
break;
+ case ISD::INTRINSIC_VOID: {
+ if (N->getConstantOperandVal(1) == Intrinsic::ppc_tdw ||
+ N->getConstantOperandVal(1) == Intrinsic::ppc_tw) {
+ unsigned Opcode = 0;
+ int16_t SImmOperand2;
+ int16_t SImmOperand3;
+ int16_t SImmOperand4;
+ SDValue Ops[3];
+ bool isOperand2IntS16Immediate =
+ isIntS16Immediate(N->getOperand(2), SImmOperand2);
+ bool isOperand3IntS16Immediate =
+ isIntS16Immediate(N->getOperand(3), SImmOperand3);
+ // Will emit TD/TW if 2nd and 3rd operands are reg + reg or imm + imm
+ if (isOperand2IntS16Immediate == isOperand3IntS16Immediate) {
+ Opcode = N->getConstantOperandVal(1) == Intrinsic::ppc_tdw ? PPC::TD
+ : PPC::TW;
+ Ops[0] = N->getOperand(4);
+ Ops[1] = N->getOperand(2);
+ Ops[2] = N->getOperand(3);
+ }
+ // Emit TDI/TWI if the 2nd and 3rd operands are reg + imm
+ else if (isOperand3IntS16Immediate) {
+ Opcode = N->getConstantOperandVal(1) == Intrinsic::ppc_tdw ? PPC::TDI
+ : PPC::TWI;
+ Ops[0] = N->getOperand(4);
+ Ops[1] = N->getOperand(2);
+ Ops[2] = getI32Imm(int(SImmOperand3) & 0xFFFF, dl);
+ }
+ // Emit TDI/TWI if the 2nd and 3rd operands are imm + reg
+ else {
+ Opcode = N->getConstantOperandVal(1) == Intrinsic::ppc_tdw ? PPC::TDI
+ : PPC::TWI;
+ // Need to convert the 4th operand(TO immediate: comparison bit) to the
+ // opposite TO immediate
+ assert(isIntS16Immediate(N->getOperand(4), SImmOperand4) &&
+ "4th operand is not an Immediate");
+ int16_t TO = int(SImmOperand4) & 0x1F;
+ // when first and second bit of TO not same, swap them
+ if ((TO & 0x1) != ((TO & 0x2) >> 1)) {
+ TO = (TO & 0x1) ? TO + 1 : TO - 1;
+ }
+ // when third and fourth bit of TO not same, swap them
+ if ((TO & 0x8) != ((TO & 0x10) >> 1)) {
+ TO = (TO & 0x8) ? TO + 8 : TO - 8;
+ }
+ Ops[0] = getI32Imm(TO, dl);
+ Ops[1] = N->getOperand(3);
+ Ops[2] = getI32Imm(int(SImmOperand2) & 0xFFFF, dl);
+ }
+ CurDAG->SelectNodeTo(N, Opcode, MVT::Other, Ops);
+ return;
+ }
+ break;
+ }
+
case ISD::INTRINSIC_WO_CHAIN: {
// We emit the PPC::FSELS instruction here because of type conflicts with
// the comparison operand. The FSELS instruction is defined to use an 8-byte
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
