achieveartificialintelligence created this revision.
achieveartificialintelligence added reviewers: HsiangKai, kito-cheng,
craig.topper, jrtc27, luismarques, asb.
Herald added subscribers: frasercrmck, apazos, sameer.abuasal, s.egerton, Jim,
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones,
zzheng, niosHD, sabuasal, simoncook, johnrusso, rbar.
achieveartificialintelligence requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D112774
Files:
clang/include/clang/Basic/BuiltinsRISCV.def
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkb.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkc.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkx.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkb.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkc.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkx.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
clang/test/Driver/riscv-arch.c
clang/test/Preprocessor/riscv-target-features.c
Index: clang/test/Preprocessor/riscv-target-features.c
===================================================================
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -28,6 +28,19 @@
// CHECK-NOT: __riscv_zbr
// CHECK-NOT: __riscv_zbs
// CHECK-NOT: __riscv_zbt
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkn
+// CHECK-NOT: __riscv_zks
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
// CHECK-NOT: __riscv_zfh
// CHECK-NOT: __riscv_v
// CHECK-NOT: __riscv_vector
@@ -189,6 +202,123 @@
// CHECK-ZBT-NOT: __riscv_b
// CHECK-ZBT-EXT: __riscv_zbt 93000
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izbkb1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-NOT: __riscv_k
+// CHECK-ZBKB-EXT: __riscv_zbkb 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izbkc1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-NOT: __riscv_k
+// CHECK-ZBKC-EXT: __riscv_zbkc 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izbkx1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-NOT: __riscv_k
+// CHECK-ZBKX-EXT: __riscv_zbkx 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izknd1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-NOT: __riscv_k
+// CHECK-ZKND-EXT: __riscv_zknd 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izkne1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-NOT: __riscv_k
+// CHECK-ZKNE-EXT: __riscv_zkne 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izknh1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-NOT: __riscv_k
+// CHECK-ZKNH-EXT: __riscv_zknh 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izksed1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-NOT: __riscv_k
+// CHECK-ZKSED-EXT: __riscv_zksed 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izksh1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-NOT: __riscv_k
+// CHECK-ZKSH-EXT: __riscv_zksh 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izkr1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-NOT: __riscv_k
+// CHECK-ZKR-EXT: __riscv_zkr 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izkn1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izkn1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKN-EXT %s
+// CHECK-ZKN-NOT: __riscv_k
+// CHECK-ZKN-EXT: __riscv_zkn 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izks1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKS-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izks1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKS-EXT %s
+// CHECK-ZKS-NOT: __riscv_k
+// CHECK-ZKS-EXT: __riscv_zks 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izkt1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-NOT: __riscv_k
+// CHECK-ZKT-EXT: __riscv_zkt 100000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izk1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-NOT: __riscv_k
+// CHECK-ZK-EXT: __riscv_zk 100000
+
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv32iv0p10 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/test/Driver/riscv-arch.c
===================================================================
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -398,6 +398,15 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
// RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkb -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBKB-NOFLAG %s
+// RV32-EXPERIMENTAL-ZBKB-NOFLAG: error: invalid arch name 'rv32izbkb'
+// RV32-EXPERIMENTAL-ZBKB-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkb1p0 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBKB %s
+// RV32-EXPERIMENTAL-ZBKB: "-target-feature" "+experimental-zbkb"
+
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
// RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zksh -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZKSH
+
+// RV64ZKSH-LABEL: @sm3p0(
+// RV64ZKSH-NEXT: entry:
+// RV64ZKSH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSH-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKSH-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKSH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sm3p0.i64.i64(i64 [[TMP0]])
+// RV64ZKSH-NEXT: ret i64 [[TMP1]]
+//
+long sm3p0(long rs1) {
+ return __builtin_riscv_sm3p0(rs1);
+}
+
+
+// RV64ZKSH-LABEL: @sm3p1(
+// RV64ZKSH-NEXT: entry:
+// RV64ZKSH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSH-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKSH-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKSH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sm3p1.i64.i64(i64 [[TMP0]])
+// RV64ZKSH-NEXT: ret i64 [[TMP1]]
+//
+long sm3p1(long rs1) {
+ return __builtin_riscv_sm3p1(rs1);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
@@ -0,0 +1,34 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zksed -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZKSED
+
+// RV64ZKSED-LABEL: @sm4ks(
+// RV64ZKSED-NEXT: entry:
+// RV64ZKSED-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSED-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSED-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKSED-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZKSED-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKSED-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZKSED-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.sm4ks.i64.i64.i8.i64(i64 [[TMP0]], i64 [[TMP1]], i8 0)
+// RV64ZKSED-NEXT: ret i64 [[TMP2]]
+//
+long sm4ks(long rs1, long rs2) {
+ return __builtin_riscv_sm4ks(rs1, rs2, 0);
+}
+
+
+// RV64ZKSED-LABEL: @sm4ed(
+// RV64ZKSED-NEXT: entry:
+// RV64ZKSED-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSED-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSED-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKSED-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZKSED-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKSED-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZKSED-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.sm4ed.i64.i64.i8.i64(i64 [[TMP0]], i64 [[TMP1]], i8 0)
+// RV64ZKSED-NEXT: ret i64 [[TMP2]]
+//
+long sm4ed(long rs1, long rs2) {
+ return __builtin_riscv_sm4ed(rs1, rs2, 0);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
@@ -0,0 +1,113 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zknh -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZKNH
+
+
+// RV64ZKNH-LABEL: @sha512sig0(
+// RV64ZKNH-NEXT: entry:
+// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig0(i64 [[CONV]])
+// RV64ZKNH-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKNH-NEXT: ret i32 [[CONV1]]
+//
+int sha512sig0(int rs1) {
+ return __builtin_riscv_sha512sig0(rs1);
+}
+
+
+// RV64ZKNH-LABEL: @sha512sig1(
+// RV64ZKNH-NEXT: entry:
+// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig1(i64 [[CONV]])
+// RV64ZKNH-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKNH-NEXT: ret i32 [[CONV1]]
+//
+int sha512sig1(int rs1) {
+ return __builtin_riscv_sha512sig1(rs1);
+}
+
+
+// RV64ZKNH-LABEL: @sha512sum0(
+// RV64ZKNH-NEXT: entry:
+// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum0(i64 [[CONV]])
+// RV64ZKNH-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKNH-NEXT: ret i32 [[CONV1]]
+//
+int sha512sum0(int rs1) {
+ return __builtin_riscv_sha512sum0(rs1);
+}
+
+
+// RV64ZKNH-LABEL: @sha512sum1(
+// RV64ZKNH-NEXT: entry:
+// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum1(i64 [[CONV]])
+// RV64ZKNH-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKNH-NEXT: ret i32 [[CONV1]]
+//
+int sha512sum1(int rs1) {
+ return __builtin_riscv_sha512sum1(rs1);
+}
+
+
+// RV64ZKNH-LABEL: @sha256sig0(
+// RV64ZKNH-NEXT: entry:
+// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sig0.i64.i64(i64 [[TMP0]])
+// RV64ZKNH-NEXT: ret i64 [[TMP1]]
+//
+long sha256sig0(long rs1) {
+ return __builtin_riscv_sha256sig0(rs1);
+}
+
+// RV64ZKNH-LABEL: @sha256sig1(
+// RV64ZKNH-NEXT: entry:
+// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sig1.i64.i64(i64 [[TMP0]])
+// RV64ZKNH-NEXT: ret i64 [[TMP1]]
+//
+long sha256sig1(long rs1) {
+ return __builtin_riscv_sha256sig1(rs1);
+}
+
+
+// RV64ZKNH-LABEL: @sha256sum0(
+// RV64ZKNH-NEXT: entry:
+// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sum0.i64.i64(i64 [[TMP0]])
+// RV64ZKNH-NEXT: ret i64 [[TMP1]]
+//
+long sha256sum0(long rs1) {
+ return __builtin_riscv_sha256sum0(rs1);
+}
+
+// RV64ZKNH-LABEL: @sha256sum1(
+// RV64ZKNH-NEXT: entry:
+// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sum1.i64.i64(i64 [[TMP0]])
+// RV64ZKNH-NEXT: ret i64 [[TMP1]]
+//
+long sha256sum1(long rs1) {
+ return __builtin_riscv_sha256sum1(rs1);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zkne -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZKNE
+
+
+// RV64ZKNE-LABEL: @aes64es(
+// RV64ZKNE-NEXT: entry:
+// RV64ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZKNE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNE-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZKNE-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
+// RV64ZKNE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64es(i64 [[CONV]], i64 [[CONV1]])
+// RV64ZKNE-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
+// RV64ZKNE-NEXT: ret i32 [[CONV2]]
+//
+int aes64es(int rs1, int rs2) {
+ return __builtin_riscv_aes64es(rs1, rs2);
+}
+
+
+// RV64ZKNE-LABEL: @aes64esm(
+// RV64ZKNE-NEXT: entry:
+// RV64ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZKNE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNE-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZKNE-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
+// RV64ZKNE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64esm(i64 [[CONV]], i64 [[CONV1]])
+// RV64ZKNE-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
+// RV64ZKNE-NEXT: ret i32 [[CONV2]]
+//
+int aes64esm(int rs1, int rs2) {
+ return __builtin_riscv_aes64esm(rs1, rs2);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
@@ -0,0 +1,88 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zknd -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZKND
+
+
+// RV64ZKND-LABEL: @es64dsm(
+// RV64ZKND-NEXT: entry:
+// RV64ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZKND-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKND-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZKND-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
+// RV64ZKND-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64dsm(i64 [[CONV]], i64 [[CONV1]])
+// RV64ZKND-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
+// RV64ZKND-NEXT: ret i32 [[CONV2]]
+//
+int es64dsm(int rs1, int rs2) {
+ return __builtin_riscv_aes64dsm(rs1, rs2);
+}
+
+
+// RV64ZKND-LABEL: @es64ds(
+// RV64ZKND-NEXT: entry:
+// RV64ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZKND-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKND-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZKND-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
+// RV64ZKND-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64ds(i64 [[CONV]], i64 [[CONV1]])
+// RV64ZKND-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
+// RV64ZKND-NEXT: ret i32 [[CONV2]]
+//
+int es64ds(int rs1, int rs2) {
+ return __builtin_riscv_aes64ds(rs1, rs2);
+}
+
+
+// RV64ZKND-LABEL: @es64im(
+// RV64ZKND-NEXT: entry:
+// RV64ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKND-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.aes64im(i64 [[CONV]])
+// RV64ZKND-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKND-NEXT: ret i32 [[CONV1]]
+//
+int es64im(int rs1) {
+ return __builtin_riscv_aes64im(rs1);
+}
+
+// RV64ZKND-LABEL: @aes64ks1i(
+// RV64ZKND-NEXT: entry:
+// RV64ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKND-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.aes64ks1i(i64 [[CONV]], i32 0)
+// RV64ZKND-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKND-NEXT: ret i32 [[CONV1]]
+//
+int aes64ks1i(int rs1) {
+ return __builtin_riscv_aes64ks1i(rs1, 0);
+}
+
+// RV64ZKND-LABEL: @aes64ks2(
+// RV64ZKND-NEXT: entry:
+// RV64ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZKND-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKND-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZKND-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
+// RV64ZKND-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64ks2(i64 [[CONV]], i64 [[CONV1]])
+// RV64ZKND-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
+// RV64ZKND-NEXT: ret i32 [[CONV2]]
+//
+int aes64ks2(int rs1, int rs2) {
+ return __builtin_riscv_aes64ks2(rs1, rs2);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkx.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkx.c
@@ -0,0 +1,35 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbkx -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZBKX
+
+// RV64ZBKX-LABEL: @xperm8(
+// RV64ZBKX-NEXT: entry:
+// RV64ZBKX-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKX-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKX-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBKX-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBKX-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBKX-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBKX-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.xperm8.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBKX-NEXT: ret i64 [[TMP2]]
+//
+long xperm8(long rs1, long rs2)
+{
+ return __builtin_riscv_xperm8(rs1, rs2);
+}
+
+// RV64ZBKX-LABEL: @xperm4(
+// RV64ZBKX-NEXT: entry:
+// RV64ZBKX-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKX-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKX-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBKX-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBKX-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBKX-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBKX-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.xperm4.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBKX-NEXT: ret i64 [[TMP2]]
+//
+long xperm4(long rs1, long rs2)
+{
+ return __builtin_riscv_xperm4(rs1, rs2);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkc.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkc.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbkc -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZBKC
+
+// RV64ZBKC-LABEL: @clmul(
+// RV64ZBKC-NEXT: entry:
+// RV64ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBKC-NEXT: ret i64 [[TMP2]]
+//
+long clmul(long a, long b) {
+ return __builtin_riscv_k_clmul(a, b);
+}
+
+// RV64ZBKC-LABEL: @clmulh(
+// RV64ZBKC-NEXT: entry:
+// RV64ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBKC-NEXT: ret i64 [[TMP2]]
+//
+long clmulh(long a, long b) {
+ return __builtin_riscv_k_clmulh(a, b);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkb.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkb.c
@@ -0,0 +1,16 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbkb -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZBKB
+
+// RV64ZBKB-LABEL: @brev8(
+// RV64ZBKB-NEXT: entry:
+// RV64ZBKB-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBKB-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
+// RV64ZBKB-NEXT: ret i32 [[TMP1]]
+//
+int brev8(int rs1)
+{
+ return __builtin_riscv_brev8(rs1);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zksh -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZKSH
+
+// RV32ZKSH-LABEL: @sm3p0(
+// RV32ZKSH-NEXT: entry:
+// RV32ZKSH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKSH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKSH-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.sm3p0.i32.i32(i32 [[TMP0]])
+// RV32ZKSH-NEXT: ret i32 [[TMP1]]
+//
+long sm3p0(long rs1)
+{
+ return __builtin_riscv_sm3p0(rs1);
+}
+
+// RV32ZKSH-LABEL: @sm3p1(
+// RV32ZKSH-NEXT: entry:
+// RV32ZKSH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKSH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKSH-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.sm3p1.i32.i32(i32 [[TMP0]])
+// RV32ZKSH-NEXT: ret i32 [[TMP1]]
+//
+long sm3p1(long rs1) {
+ return __builtin_riscv_sm3p1(rs1);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
@@ -0,0 +1,34 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zksed -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZKSED
+
+// RV32ZKSED-LABEL: @sm4ks(
+// RV32ZKSED-NEXT: entry:
+// RV32ZKSED-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ks.i32.i32.i8.i32(i32 [[TMP0]], i32 [[TMP1]], i8 0)
+// RV32ZKSED-NEXT: ret i32 [[TMP2]]
+//
+long sm4ks(long rs1, long rs2) {
+ return __builtin_riscv_sm4ks(rs1, rs2, 0);
+}
+
+
+// RV32ZKSED-LABEL: @sm4ed(
+// RV32ZKSED-NEXT: entry:
+// RV32ZKSED-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ed.i32.i32.i8.i32(i32 [[TMP0]], i32 [[TMP1]], i8 0)
+// RV32ZKSED-NEXT: ret i32 [[TMP2]]
+//
+long sm4ed(long rs1, long rs2) {
+ return __builtin_riscv_sm4ed(rs1, rs2, 0);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
@@ -0,0 +1,148 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zknh -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZKNH
+
+// RV32ZKNH-LABEL: @sha512sig0l(
+// RV32ZKNH-NEXT: entry:
+// RV32ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sig0l(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT: ret i32 [[TMP2]]
+//
+int sha512sig0l(int rs1, int rs2) {
+ return __builtin_riscv_sha512sig0l(rs1, rs2);
+}
+
+
+// RV32ZKNH-LABEL: @sha512sig0h(
+// RV32ZKNH-NEXT: entry:
+// RV32ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sig0h(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT: ret i32 [[TMP2]]
+//
+int sha512sig0h(int rs1, int rs2) {
+ return __builtin_riscv_sha512sig0h(rs1, rs2);
+}
+
+
+// RV32ZKNH-LABEL: @sha512sig1l(
+// RV32ZKNH-NEXT: entry:
+// RV32ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sig1l(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT: ret i32 [[TMP2]]
+//
+int sha512sig1l(int rs1, int rs2) {
+ return __builtin_riscv_sha512sig1l(rs1, rs2);
+}
+
+// RV32ZKNH-LABEL: @sha512sig1h(
+// RV32ZKNH-NEXT: entry:
+// RV32ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sig1h(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT: ret i32 [[TMP2]]
+//
+int sha512sig1h(int rs1, int rs2) {
+ return __builtin_riscv_sha512sig1h(rs1, rs2);
+}
+
+// RV32ZKNH-LABEL: @sha512sum0r(
+// RV32ZKNH-NEXT: entry:
+// RV32ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sum0r(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT: ret i32 [[TMP2]]
+//
+int sha512sum0r(int rs1, int rs2) {
+ return __builtin_riscv_sha512sum0r(rs1, rs2);
+}
+
+
+// RV32ZKNH-LABEL: @sha512sum1r(
+// RV32ZKNH-NEXT: entry:
+// RV32ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sum1r(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT: ret i32 [[TMP2]]
+//
+int sha512sum1r(int rs1, int rs2) {
+ return __builtin_riscv_sha512sum1r(rs1, rs2);
+}
+
+
+// RV32ZKNH-LABEL: @sha256sig0(
+// RV32ZKNH-NEXT: entry:
+// RV32ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sig0.i32.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT: ret i32 [[TMP1]]
+//
+long sha256sig0(long rs1) {
+ return __builtin_riscv_sha256sig0(rs1);
+}
+
+
+// RV32ZKNH-LABEL: @sha256sig1(
+// RV32ZKNH-NEXT: entry:
+// RV32ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sig1.i32.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT: ret i32 [[TMP1]]
+//
+long sha256sig1(long rs1) {
+ return __builtin_riscv_sha256sig1(rs1);
+}
+
+
+// RV32ZKNH-LABEL: @sha256sum0(
+// RV32ZKNH-NEXT: entry:
+// RV32ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sum0.i32.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT: ret i32 [[TMP1]]
+//
+long sha256sum0(long rs1) {
+ return __builtin_riscv_sha256sum0(rs1);
+}
+
+
+// RV32ZKNH-LABEL: @sha256sum1(
+// RV32ZKNH-NEXT: entry:
+// RV32ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sum1.i32.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT: ret i32 [[TMP1]]
+//
+long sha256sum1(long rs1) {
+ return __builtin_riscv_sha256sum1(rs1);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zkne -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZKNE
+
+// RV32ZKNE-LABEL: @aes32esi(
+// RV32ZKNE-NEXT: entry:
+// RV32ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32esi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
+// RV32ZKNE-NEXT: ret i32 [[TMP2]]
+//
+int aes32esi(int rs1, int rs2) {
+ return __builtin_riscv_aes32esi(rs1, rs2, 3);
+}
+
+// RV32ZKNE-LABEL: @aes32esmi(
+// RV32ZKNE-NEXT: entry:
+// RV32ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32esmi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
+// RV32ZKNE-NEXT: ret i32 [[TMP2]]
+//
+int aes32esmi(int rs1, int rs2) {
+ return __builtin_riscv_aes32esmi(rs1, rs2, 3);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zknd -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZKND
+
+// RV32ZKND-LABEL: @aes32dsi(
+// RV32ZKND-NEXT: entry:
+// RV32ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKND-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKND-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKND-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKND-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKND-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKND-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
+// RV32ZKND-NEXT: ret i32 [[TMP2]]
+//
+int aes32dsi(int rs1, int rs2) {
+ return __builtin_riscv_aes32dsi(rs1, rs2, 3);
+}
+
+// RV32ZKND-LABEL: @aes32dsmi(
+// RV32ZKND-NEXT: entry:
+// RV32ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKND-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKND-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKND-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKND-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKND-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKND-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsmi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
+// RV32ZKND-NEXT: ret i32 [[TMP2]]
+//
+int aes32dsmi(int rs1, int rs2) {
+ return __builtin_riscv_aes32dsmi(rs1, rs2, 3);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkx.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkx.c
@@ -0,0 +1,35 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbkx -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZBKX
+
+// RV32ZBKX-LABEL: @xperm8(
+// RV32ZBKX-NEXT: entry:
+// RV32ZBKX-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKX-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKX-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBKX-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBKX-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBKX-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBKX-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.xperm8.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBKX-NEXT: ret i32 [[TMP2]]
+//
+long xperm8(long rs1, long rs2)
+{
+ return __builtin_riscv_xperm8(rs1, rs2);
+}
+
+// RV32ZBKX-LABEL: @xperm4(
+// RV32ZBKX-NEXT: entry:
+// RV32ZBKX-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKX-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKX-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBKX-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBKX-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBKX-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBKX-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.xperm4.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBKX-NEXT: ret i32 [[TMP2]]
+//
+long xperm4(long rs1, long rs2)
+{
+ return __builtin_riscv_xperm4(rs1, rs2);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkc.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkc.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbkc -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZBKC
+
+// RV32ZBKC-LABEL: @clmul(
+// RV32ZBKC-NEXT: entry:
+// RV32ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBKC-NEXT: ret i32 [[TMP2]]
+//
+long clmul(long a, long b) {
+ return __builtin_riscv_k_clmul(a, b);
+}
+
+// RV32ZBKC-LABEL: @clmulh(
+// RV32ZBKC-NEXT: entry:
+// RV32ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBKC-NEXT: ret i32 [[TMP2]]
+//
+long clmulh(long a, long b) {
+ return __builtin_riscv_k_clmulh(a, b);
+}
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkb.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkb.c
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbkb -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZBKB
+
+// RV32ZBKB-LABEL: @brev8(
+// RV32ZBKB-NEXT: entry:
+// RV32ZBKB-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKB-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
+// RV32ZBKB-NEXT: ret i32 [[TMP1]]
+//
+int brev8(int rs1)
+{
+ return __builtin_riscv_brev8(rs1);
+}
+
+// RV32ZBKB-LABEL: @zip(
+// RV32ZBKB-NEXT: entry:
+// RV32ZBKB-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKB-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.zip.i32(i32 [[TMP0]])
+// RV32ZBKB-NEXT: ret i32 [[TMP1]]
+//
+int zip(int rs1)
+{
+ return __builtin_riscv_zip(rs1);
+}
+
+// RV32ZBKB-LABEL: @unzip(
+// RV32ZBKB-NEXT: entry:
+// RV32ZBKB-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKB-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.unzip.i32(i32 [[TMP0]])
+// RV32ZBKB-NEXT: ret i32 [[TMP1]]
+//
+int unzip(int rs1)
+{
+ return __builtin_riscv_unzip(rs1);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -18613,7 +18613,14 @@
case RISCV::BI__builtin_riscv_crc32c_b:
case RISCV::BI__builtin_riscv_crc32c_h:
case RISCV::BI__builtin_riscv_crc32c_w:
- case RISCV::BI__builtin_riscv_crc32c_d: {
+ case RISCV::BI__builtin_riscv_crc32c_d:
+ case RISCV::BI__builtin_riscv_brev8:
+ case RISCV::BI__builtin_riscv_zip:
+ case RISCV::BI__builtin_riscv_unzip:
+ case RISCV::BI__builtin_riscv_xperm8:
+ case RISCV::BI__builtin_riscv_xperm4:
+ case RISCV::BI__builtin_riscv_k_clmul:
+ case RISCV::BI__builtin_riscv_k_clmulh: {
switch (BuiltinID) {
default: llvm_unreachable("unexpected builtin ID");
// Zbb
@@ -18698,6 +18705,33 @@
case RISCV::BI__builtin_riscv_crc32c_d:
ID = Intrinsic::riscv_crc32c_d;
break;
+
+ // zbkb
+ case RISCV::BI__builtin_riscv_brev8:
+ ID = Intrinsic::riscv_brev8;
+ break;
+ case RISCV::BI__builtin_riscv_zip:
+ ID = Intrinsic::riscv_zip;
+ break;
+ case RISCV::BI__builtin_riscv_unzip:
+ ID = Intrinsic::riscv_unzip;
+ break;
+
+ // Zbkc
+ case RISCV::BI__builtin_riscv_k_clmul:
+ ID = Intrinsic::riscv_clmul;
+ break;
+ case RISCV::BI__builtin_riscv_k_clmulh:
+ ID = Intrinsic::riscv_clmulh;
+ break;
+
+ // zbkx
+ case RISCV::BI__builtin_riscv_xperm8:
+ ID = Intrinsic::riscv_xperm8;
+ break;
+ case RISCV::BI__builtin_riscv_xperm4:
+ ID = Intrinsic::riscv_xperm4;
+ break;
}
IntrinsicTypes = {ResultType};
@@ -18705,6 +18739,112 @@
}
// Vector builtins are handled from here.
#include "clang/Basic/riscv_vector_builtin_cg.inc"
+
+ case RISCV::BI__builtin_riscv_aes32dsi:
+ ID = Intrinsic::riscv_aes32dsi;
+ break;
+ case RISCV::BI__builtin_riscv_aes32dsmi:
+ ID = Intrinsic::riscv_aes32dsmi;
+ break;
+ case RISCV::BI__builtin_riscv_aes32esi:
+ ID = Intrinsic::riscv_aes32esi;
+ break;
+ case RISCV::BI__builtin_riscv_aes32esmi:
+ ID = Intrinsic::riscv_aes32esmi;
+ break;
+ case RISCV::BI__builtin_riscv_aes64ds:
+ ID = Intrinsic::riscv_aes64ds;
+ break;
+ case RISCV::BI__builtin_riscv_aes64dsm:
+ ID = Intrinsic::riscv_aes64dsm;
+ break;
+ case RISCV::BI__builtin_riscv_aes64es:
+ ID = Intrinsic::riscv_aes64es;
+ break;
+ case RISCV::BI__builtin_riscv_aes64esm:
+ ID = Intrinsic::riscv_aes64esm;
+ break;
+ case RISCV::BI__builtin_riscv_aes64im:
+ ID = Intrinsic::riscv_aes64im;
+ break;
+ case RISCV::BI__builtin_riscv_aes64ks1i:
+ ID = Intrinsic::riscv_aes64ks1i;
+ break;
+ case RISCV::BI__builtin_riscv_aes64ks2:
+ ID = Intrinsic::riscv_aes64ks2;
+ break;
+ case RISCV::BI__builtin_riscv_getnoise:
+ ID = Intrinsic::riscv_getnoise;
+ IntrinsicTypes = {ResultType};
+ break;
+ case RISCV::BI__builtin_riscv_pollentropy:
+ ID = Intrinsic::riscv_pollentropy;
+ IntrinsicTypes = {ResultType};
+ break;
+ case RISCV::BI__builtin_riscv_sha256sig0:
+ ID = Intrinsic::riscv_sha256sig0;
+ IntrinsicTypes = {Ops[0]->getType(), ResultType};
+ break;
+ case RISCV::BI__builtin_riscv_sha256sig1:
+ ID = Intrinsic::riscv_sha256sig1;
+ IntrinsicTypes = {Ops[0]->getType(), ResultType};
+ break;
+ case RISCV::BI__builtin_riscv_sha256sum0:
+ ID = Intrinsic::riscv_sha256sum0;
+ IntrinsicTypes = {Ops[0]->getType(), ResultType};
+ break;
+ case RISCV::BI__builtin_riscv_sha256sum1:
+ ID = Intrinsic::riscv_sha256sum1;
+ IntrinsicTypes = {Ops[0]->getType(), ResultType};
+ break;
+ case RISCV::BI__builtin_riscv_sha512sig0:
+ ID = Intrinsic::riscv_sha512sig0;
+ break;
+ case RISCV::BI__builtin_riscv_sha512sig0h:
+ ID = Intrinsic::riscv_sha512sig0h;
+ break;
+ case RISCV::BI__builtin_riscv_sha512sig0l:
+ ID = Intrinsic::riscv_sha512sig0l;
+ break;
+ case RISCV::BI__builtin_riscv_sha512sig1:
+ ID = Intrinsic::riscv_sha512sig1;
+ break;
+ case RISCV::BI__builtin_riscv_sha512sig1h:
+ ID = Intrinsic::riscv_sha512sig1h;
+ break;
+ case RISCV::BI__builtin_riscv_sha512sig1l:
+ ID = Intrinsic::riscv_sha512sig1l;
+ break;
+ case RISCV::BI__builtin_riscv_sha512sum0:
+ ID = Intrinsic::riscv_sha512sum0;
+ break;
+ case RISCV::BI__builtin_riscv_sha512sum0r:
+ ID = Intrinsic::riscv_sha512sum0r;
+ break;
+ case RISCV::BI__builtin_riscv_sha512sum1:
+ ID = Intrinsic::riscv_sha512sum1;
+ break;
+ case RISCV::BI__builtin_riscv_sha512sum1r:
+ ID = Intrinsic::riscv_sha512sum1r;
+ break;
+ case RISCV::BI__builtin_riscv_sm3p0:
+ ID = Intrinsic::riscv_sm3p0;
+ IntrinsicTypes = {Ops[0]->getType(), ResultType};
+ break;
+ case RISCV::BI__builtin_riscv_sm3p1:
+ ID = Intrinsic::riscv_sm3p1;
+ IntrinsicTypes = {Ops[0]->getType(), ResultType};
+ break;
+ case RISCV::BI__builtin_riscv_sm4ed:
+ ID = Intrinsic::riscv_sm4ed;
+ IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[2]->getType(),
+ ResultType};
+ break;
+ case RISCV::BI__builtin_riscv_sm4ks:
+ ID = Intrinsic::riscv_sm4ks;
+ IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[2]->getType(),
+ ResultType};
+ break;
}
assert(ID != Intrinsic::not_intrinsic);
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -181,6 +181,12 @@
if (ISAInfo->hasExtension("v"))
Builder.defineMacro("__riscv_vector");
+
+ if (ISAInfo->hasExtension("zknd") || ISAInfo->hasExtension("zkne") ||
+ ISAInfo->hasExtension("zknh") || ISAInfo->hasExtension("zksh") ||
+ ISAInfo->hasExtension("zksed") || ISAInfo->hasExtension("zkr") ||
+ ISAInfo->hasExtension("zk"))
+ Builder.defineMacro("__riscv_crypto");
}
const Builtin::Info RISCVTargetInfo::BuiltinInfo[] = {
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===================================================================
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -57,5 +57,61 @@
TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr")
TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr")
+// zbkb extension
+TARGET_BUILTIN(__builtin_riscv_brev8, "ZiZi", "nc", "experimental-zbkb")
+TARGET_BUILTIN(__builtin_riscv_zip, "ZiZi", "nc", "experimental-zbkb")
+TARGET_BUILTIN(__builtin_riscv_unzip, "ZiZi", "nc", "experimental-zbkb")
+
+// zbkc extension
+TARGET_BUILTIN(__builtin_riscv_k_clmul, "LiLiLi", "nc", "experimental-zbkc")
+TARGET_BUILTIN(__builtin_riscv_k_clmulh, "LiLiLi", "nc", "experimental-zbkc")
+
+// zbkx extension
+TARGET_BUILTIN(__builtin_riscv_xperm8, "LiLiLi", "nc", "experimental-zbkx")
+TARGET_BUILTIN(__builtin_riscv_xperm4, "LiLiLi", "nc", "experimental-zbkx")
+
+// zknd extension
+TARGET_BUILTIN(__builtin_riscv_aes32dsi, "LiLiLiUc", "nc", "experimental-zknd")
+TARGET_BUILTIN(__builtin_riscv_aes32dsmi, "ZiZiZiUc", "nc", "experimental-zknd")
+TARGET_BUILTIN(__builtin_riscv_aes64ds, "WiWiWi", "nc", "experimental-zknd")
+TARGET_BUILTIN(__builtin_riscv_aes64dsm, "WiWiWi", "nc", "experimental-zknd")
+TARGET_BUILTIN(__builtin_riscv_aes64im, "WiWi", "nc", "experimental-zknd")
+TARGET_BUILTIN(__builtin_riscv_aes64ks1i, "WiWiUi", "nc", "experimental-zknd")
+TARGET_BUILTIN(__builtin_riscv_aes64ks2, "WiWiWi", "nc", "experimental-zknd")
+
+// zkne extension
+TARGET_BUILTIN(__builtin_riscv_aes32esi, "ZiZiZiUc", "nc", "experimental-zkne")
+TARGET_BUILTIN(__builtin_riscv_aes32esmi, "ZiZiZiUc", "nc", "experimental-zkne")
+TARGET_BUILTIN(__builtin_riscv_aes64es, "WiWiWi", "nc", "experimental-zkne")
+TARGET_BUILTIN(__builtin_riscv_aes64esm, "WiWiWi", "nc", "experimental-zkne")
+
+// zknh extension
+TARGET_BUILTIN(__builtin_riscv_sha256sig0, "LiLi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha256sig1, "LiLi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha256sum0, "LiLi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha256sum1, "LiLi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sig0, "WiWi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sig0h, "ZiZiZi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sig0l, "ZiZiZi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sig1, "WiWi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sig1h, "ZiZiZi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sig1l, "ZiZiZi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sum0, "WiWi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sum0r, "ZiZiZi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sum1, "WiWi", "nc", "experimental-zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sum1r, "ZiZiZi", "nc", "experimental-zknh")
+
+// zkr extension
+TARGET_BUILTIN(__builtin_riscv_getnoise, "Li", "nc", "experimental-zkr")
+TARGET_BUILTIN(__builtin_riscv_pollentropy, "Li", "nc", "experimental-zkr")
+
+// zksh extension
+TARGET_BUILTIN(__builtin_riscv_sm3p0, "LiLi", "nc", "experimental-zksh")
+TARGET_BUILTIN(__builtin_riscv_sm3p1, "LiLi", "nc", "experimental-zksh")
+
+// zksed extension
+TARGET_BUILTIN(__builtin_riscv_sm4ed, "LiLiLiUc", "nc", "experimental-zksed")
+TARGET_BUILTIN(__builtin_riscv_sm4ks, "LiLiLiUc", "nc", "experimental-zksed")
+
#undef BUILTIN
#undef TARGET_BUILTIN
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