dmgreen added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64.td:689
+ "Cortex-X2 ARM processors", [
+ FeatureFuseAES,
+ FeaturePostRAScheduler]>;
----------------
According to the software optimization guide, we can enable FeatureCmpBccFusion
too.
================
Comment at: llvm/lib/Target/AArch64/AArch64Subtarget.cpp:105
case CortexX1:
+ case CortexX2:
PrefFunctionLogAlignment = 4;
----------------
This can be a new block with VScaleForTuning = 1 (I think) and the
PrefFunctionLogAlignment.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D112459/new/
https://reviews.llvm.org/D112459
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