Author: Kamau Bridgeman Date: 2021-10-13T09:40:06-05:00 New Revision: 89ec99c778943151213118f096e8008197c9ba10
URL: https://github.com/llvm/llvm-project/commit/89ec99c778943151213118f096e8008197c9ba10 DIFF: https://github.com/llvm/llvm-project/commit/89ec99c778943151213118f096e8008197c9ba10.diff LOG: [PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameter The builtin __rlwnm is currently constrained to accept only constants for the shift parameter but the instructions emitted for it have no such constraint, this patch allows the builtins to accept variable shift. Reviewed By: NeHuang, amyk Differential Revision: https://reviews.llvm.org/D111229 Added: Modified: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Sema/SemaChecking.cpp clang/test/CodeGen/builtins-ppc-xlcompat-error.c clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def index 3fa5729fc7d03..f82d455506860 100644 --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -117,7 +117,7 @@ BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "") BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "") BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "") // Rotate -BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "") +BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "") BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "") BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "") // load diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 4d84606290b4e..090fcd985df07 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -3432,8 +3432,7 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, // For __rlwnm, __rlwimi and __rldimi, the last parameter mask must // be a constant that represents a contiguous bit field. case PPC::BI__builtin_ppc_rlwnm: - return SemaBuiltinConstantArg(TheCall, 1, Result) || - SemaValueIsRunOfOnes(TheCall, 2); + return SemaValueIsRunOfOnes(TheCall, 2); case PPC::BI__builtin_ppc_rlwimi: case PPC::BI__builtin_ppc_rldimi: return SemaBuiltinConstantArg(TheCall, 2, Result) || diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c index 9fc218b1de413..5f57d7575c859 100644 --- a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c +++ b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c @@ -41,10 +41,8 @@ void test_builtin_ppc_rlwimi() { } void test_builtin_ppc_rlwnm() { - unsigned int shift; unsigned int mask; - unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}} - res = __builtin_ppc_rlwnm(ui, 31, mask); // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}} + unsigned int res = __builtin_ppc_rlwnm(ui, 31, mask); // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}} res = __builtin_ppc_rlwnm(ui, 31, 0xFF0F0F00); // expected-error {{argument 2 value should represent a contiguous bit field}} } diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c b/clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c index 5ca7706f422ff..73c2d2cb8aee2 100644 --- a/clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c +++ b/clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c @@ -56,6 +56,22 @@ void test_builtin_ppc_rlwnm() { unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF); } +void test_builtin_ppc_rlwnm2(unsigned int shift) { + // CHECK-LABEL: test_builtin_ppc_rlwnm2 + // CHECK: %shift.addr = alloca i32, align 4 + // CHECK-NEXT: %res = alloca i32, align 4 + // CHECK-NEXT: store i32 %shift, i32* %shift.addr, align 4 + // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, i32* @ui, align 4 + // CHECK-NEXT: [[RB:%[0-9]+]] = load i32, i32* %shift.addr, align 4 + // CHECK-NEXT: [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 [[RB]]) + // CHECK-NEXT: [[RD:%[0-9]+]] = and i32 [[RC]], 511 + // CHECK-NEXT: store i32 [[RD]], i32* %res, align 4 + // CHECK-NEXT: ret void + + /*mask = 0x1FF = 511*/ + unsigned int res = __builtin_ppc_rlwnm(ui, shift, 0x1FF); +} + // CHECK-LABEL: @testrotatel4( // CHECK: [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 {{%.*}}, i32 {{%.*}}) // CHECK-NEXT: ret i32 [[TMP]] _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
