nemanjai requested changes to this revision.
nemanjai added a comment.
This revision now requires changes to proceed.

There isn't enough information in the test to determine whether this adequately 
improves code generation (in fact, whether it improves code generation at all).



================
Comment at: llvm/test/CodeGen/PowerPC/test-vector-insert.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
----------------
Test cases where we improve code generation should be pre-committed as an NFC 
change so that the review shows just the differences in code generation. It is 
not easy to evaluate whether the patch improves the code or not without seeing 
how it changed.


================
Comment at: llvm/test/CodeGen/PowerPC/test-vector-insert.ll:5
+; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE-P8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
----------------
Code generation on Power9 is important as well. Please add that test.


================
Comment at: llvm/test/CodeGen/PowerPC/test-vector-insert.ll:15
+; xscvdpsxws and uxws is only available on Power7 and above
+; Codgen is different for LE Power7 and Power8
+
----------------
nit: s/Codgen/Codegen


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109902/new/

https://reviews.llvm.org/D109902

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