Anastasia added inline comments.
================
Comment at: clang/lib/CodeGen/TargetInfo.cpp:10221
+ABIArgInfo SPIRABIInfo::classifyKernelArgumentType(QualType Ty) const {
+ if (getContext().getLangOpts().HIP && getTarget().getTriple().isSPIRV()) {
+ // Coerce pointer arguments with default address space to CrossWorkGroup
----------------
It feels like this needs to be in `SPIRVABIInfo` or something? Or can this be
generalized to both - SPIR and SPIR-V?
================
Comment at: clang/lib/CodeGen/TargetInfo.cpp:10224
+ // pointers for HIPSPV. When the language mode is HIP, the SPIRTargetInfo
+ // maps cuda_device to SPIR-V's CrossWorkGroup address space.
+ llvm::Type *LTy = CGT.ConvertType(Ty);
----------------
Can you explain why this mapping is needed? We already have an address space
map to perform the mapping of address spaces b/w language and target. It would
be good if we don't replicate similar logic in too many places.
================
Comment at: clang/lib/CodeGen/TargetInfo.cpp:10271
+ if (getABIInfo().getContext().getLangOpts().HIP &&
+ getABIInfo().getTarget().getTriple().isSPIRV()) {
+ FT = getABIInfo().getContext().adjustFunctionType(
----------------
Again this feels like we need `SPIRVTargetCodeGenInfo` unless the logic is
generalizable to both.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109818/new/
https://reviews.llvm.org/D109818
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