NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, lei, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton, hiraditya, qcolombet.
NeHuang requested review of this revision.
This patch marks splat immediate instructions `XXSPLTIDP` and `XXSPLTI32DX` as
rematerializable to prevent MachineLICM from moving them out of loops.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D108823
Files:
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/constant-pool.ll
llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
llvm/test/CodeGen/PowerPC/p10-splatImm.ll
Index: llvm/test/CodeGen/PowerPC/p10-splatImm.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/p10-splatImm.ll
+++ llvm/test/CodeGen/PowerPC/p10-splatImm.ll
@@ -249,7 +249,6 @@
; CHECK-LABEL: testFloatScalar:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltidp vs1, 1135290941
-; CHECK-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-NEXT: blr
entry:
@@ -270,7 +269,6 @@
; CHECK-LABEL: testDoubleRepresentableScalar:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltidp vs1, 1135290941
-; CHECK-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-NEXT: blr
entry:
Index: llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
+++ llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
@@ -35,8 +35,7 @@
define dso_local void @P10_Spill_CR_UN(%2* %arg, %1* %arg1, i32 %arg2) local_unnamed_addr {
; CHECK-LABEL: P10_Spill_CR_UN:
-; CHECK: .localentry P10_Spill_CR_UN, 1
-; CHECK-NEXT: # %bb.0: # %bb
+; CHECK: # %bb.0: # %bb
; CHECK-NEXT: mflr r0
; CHECK-NEXT: mfcr r12
; CHECK-NEXT: std r0, 16(r1)
@@ -146,19 +145,19 @@
; CHECK-NEXT: # implicit-def: $r3
; CHECK-NEXT: .LBB0_15: # %bb50
; CHECK-NEXT: li r4, 0
-; CHECK-NEXT: xxspltidp vs3, -1082130432
; CHECK-NEXT: extsh r9, r3
; CHECK-NEXT: extsw r6, r28
; CHECK-NEXT: li r5, 0
+; CHECK-NEXT: xxspltidp vs3, -1082130432
+; CHECK-NEXT: xxspltidp vs4, -1082130432
; CHECK-NEXT: std r30, 104(r1)
; CHECK-NEXT: std r29, 96(r1)
; CHECK-NEXT: li r7, 0
; CHECK-NEXT: li r8, 0
; CHECK-NEXT: li r10, 0
-; CHECK-NEXT: fmr f4, f3
-; CHECK-NEXT: xxlxor f1, f1, f1
; CHECK-NEXT: std r4, 152(r1)
; CHECK-NEXT: li r4, -1
+; CHECK-NEXT: xxlxor f1, f1, f1
; CHECK-NEXT: std r4, 112(r1)
; CHECK-NEXT: li r4, 1024
; CHECK-NEXT: bl call_4@notoc
@@ -304,19 +303,19 @@
; CHECK-BE-NEXT: # implicit-def: $r3
; CHECK-BE-NEXT: .LBB0_15: # %bb50
; CHECK-BE-NEXT: li r4, 0
-; CHECK-BE-NEXT: xxspltidp vs3, -1082130432
; CHECK-BE-NEXT: extsh r9, r3
; CHECK-BE-NEXT: extsw r6, r28
; CHECK-BE-NEXT: li r5, 0
+; CHECK-BE-NEXT: xxspltidp vs3, -1082130432
+; CHECK-BE-NEXT: xxspltidp vs4, -1082130432
; CHECK-BE-NEXT: std r30, 120(r1)
; CHECK-BE-NEXT: std r29, 112(r1)
; CHECK-BE-NEXT: li r7, 0
; CHECK-BE-NEXT: li r8, 0
; CHECK-BE-NEXT: li r10, 0
-; CHECK-BE-NEXT: fmr f4, f3
-; CHECK-BE-NEXT: xxlxor f1, f1, f1
; CHECK-BE-NEXT: std r4, 168(r1)
; CHECK-BE-NEXT: li r4, -1
+; CHECK-BE-NEXT: xxlxor f1, f1, f1
; CHECK-BE-NEXT: std r4, 128(r1)
; CHECK-BE-NEXT: li r4, 1024
; CHECK-BE-NEXT: bl call_4
Index: llvm/test/CodeGen/PowerPC/constant-pool.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/constant-pool.ll
+++ llvm/test/CodeGen/PowerPC/constant-pool.ll
@@ -364,15 +364,15 @@
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset v31, -16
+; CHECK-NEXT: xxlxor f4, f4, f4
+; CHECK-NEXT: xxsplti32dx vs3, 0, 1074935889
; CHECK-NEXT: stxv vs63, 32(r1) # 16-byte Folded Spill
; CHECK-NEXT: xxsplti32dx vs63, 0, 1074935889
-; CHECK-NEXT: xxlxor f4, f4, f4
-; CHECK-NEXT: xxlor vs3, vs63, vs63
; CHECK-NEXT: xxsplti32dx vs3, 1, -343597384
; CHECK-NEXT: # kill: def $f3 killed $f3 killed $vsl3
; CHECK-NEXT: bl __gcc_qadd@notoc
-; CHECK-NEXT: xxlor vs3, vs63, vs63
; CHECK-NEXT: xxlxor f4, f4, f4
+; CHECK-NEXT: xxsplti32dx vs3, 0, 1074935889
; CHECK-NEXT: xxsplti32dx vs3, 1, -1719329096
; CHECK-NEXT: # kill: def $f3 killed $f3 killed $vsl3
; CHECK-NEXT: bl __gcc_qadd@notoc
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1861,15 +1861,6 @@
}
let Predicates = [PrefixInstrs] in {
- def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
- (ins i32imm:$IMM32),
- "xxspltiw $XT, $IMM32", IIC_VecGeneral,
- []>;
- def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
- (ins i32imm:$IMM32),
- "xxspltidp $XT, $IMM32", IIC_VecGeneral,
- [(set v2f64:$XT,
- (PPCxxspltidp i32:$IMM32))]>;
def XXPERMX :
8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
vsrc:$XC, u3imm:$UIM),
@@ -1895,7 +1886,16 @@
// XXSPLI32DX needs extra flags to make sure the compiler does not attempt
// to spill part of the instruction when the values are similar.
-let isReMaterializable = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in {
+ def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
+ (ins i32imm:$IMM32),
+ "xxspltiw $XT, $IMM32", IIC_VecGeneral,
+ []>;
+ def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
+ (ins i32imm:$IMM32),
+ "xxspltidp $XT, $IMM32", IIC_VecGeneral,
+ [(set v2f64:$XT,
+ (PPCxxspltidp i32:$IMM32))]>;
def XXSPLTI32DX :
8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),
(ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32),
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1109,6 +1109,8 @@
case PPC::XXLXORdpz:
case PPC::XXLEQVOnes:
case PPC::XXSPLTI32DX:
+ case PPC::XXSPLTIW:
+ case PPC::XXSPLTIDP:
case PPC::V_SET0B:
case PPC::V_SET0H:
case PPC::V_SET0:
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