pengfei added inline comments.
================
Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:4478
+ let Predicates = [HasFP16] in {
+ def VMOVSHZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
+ (ins VR128X:$src1, VR128X:$src2),
----------------
craig.topper wrote:
> pengfei wrote:
> > LuoYuanke wrote:
> > > Sorry, I forgot what REV stand for. Do you know it?
> > > Is this just encoding difference for register operand compared with
> > > VMOVSHZrr? What is it used for?
> > I think REV is short for revert. Which allows a different encoding when
> > operands order are reverted.
> > Yes. It's used for a different encoding.
> It is short for "reverse". Meaing the operands are in the reversed order.
> There are two valid encodings moving from one register to another. This
> happens because there are separate opcodes for moving register to
> memory(Store) and moving memory to register(load). The memory operand for
> both of those opcodes can be a register as well. The assembler and isel
> always uses the register to register version of the load opcode. The reversed
> version is only used by the disassembler
>
> There is an exception to that. For VEX encoded AVX/AVX2 instructions,
> X86MCInstLowering will use an _REV move if it allows a 2 byte VEX prefix
> instead of a 3 byte VEX prefix. This doesn't apply to any AVX512 instructions
> though.
Thanks Craig for the information.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105263/new/
https://reviews.llvm.org/D105263
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
