[PATCH] D107647: Remove depracated built-ins for MMA and replace with new built-ins

[Ahsan Saghir via Phabricator via cfe-commits]

saghir created this revision.
Herald added subscribers: kbarton, hiraditya, nemanjai, qcolombet, MatzeB.
saghir requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107647

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/SemaCXX/ppc-pair-mma-types.cpp
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/mma-outer-product.ll
  llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
  llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
  llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll


Index: llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
+++ llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
@@ -254,17 +254,17 @@
   %i48 = bitcast <2 x double> %i44 to <16 x i8>
   %i49 = bitcast <2 x double> %i40 to <16 x i8>
   %i50 = bitcast <2 x double> %i38 to <16 x i8>
-  %i51 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i48, <16 x i8> %i49, <16 x i8> %i50)
+  %i51 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> zeroinitializer, <16 x i8> %i48, <16 x i8> %i49, <16 x i8> %i50)
   %i52 = bitcast <2 x double> %i45 to <16 x i8>
   %i53 = bitcast <2 x double> %i41 to <16 x i8>
   %i54 = bitcast <2 x double> %i39 to <16 x i8>
-  %i55 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i52, <16 x i8> %i53, <16 x i8> %i54)
+  %i55 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> zeroinitializer, <16 x i8> %i52, <16 x i8> %i53, <16 x i8> %i54)
   %i56 = bitcast <2 x double> %i46 to <16 x i8>
   %i57 = bitcast <2 x double> %i42 to <16 x i8>
-  %i58 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i56, <16 x i8> %i57, <16 x i8> %i56)
+  %i58 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> zeroinitializer, <16 x i8> %i56, <16 x i8> %i57, <16 x i8> %i56)
   %i59 = bitcast <2 x double> %i47 to <16 x i8>
   %i60 = bitcast <2 x double> %i43 to <16 x i8>
-  %i61 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i59, <16 x i8> %i60, <16 x i8> %i59)
+  %i61 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> zeroinitializer, <16 x i8> %i59, <16 x i8> %i60, <16 x i8> %i59)
   %i62 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i51, <256 x i1> undef, <16 x i8> undef)
   %i63 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i55, <256 x i1> undef, <16 x i8> undef)
   %i64 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i58, <256 x i1> undef, <16 x i8> undef)
@@ -327,7 +327,7 @@
 }
 
 declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
-declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+declare <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)
 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
 
Index: llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
+++ llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
@@ -11,12 +11,12 @@
 ; CHECK-NEXT:    xxlor vs3, v2, v2
 ; CHECK-NEXT:    stxv vs1, 0(0)
 dmblvi_entry:
-  %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
+  %0 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
   %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
   %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
   store <16 x i8> %2, <16 x i8>* null, align 1
   unreachable
 }
 
-declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+declare <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -16,7 +16,7 @@
 ; when MMA is disabled.
 
 ; assemble_pair
-declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
+declare <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8>, <16 x i8>)
 define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_pair:
 ; CHECK:       # %bb.0: # %entry
@@ -46,7 +46,7 @@
 ; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r3)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
-  %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
+  %0 = tail call <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8> %vc, <16 x i8> %vc)
   store <256 x i1> %0, <256 x i1>* %ptr, align 32
   ret void
 }
Index: llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
+++ llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
@@ -6,7 +6,7 @@
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
 
-declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
+declare <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8>, <16 x i8>)
 declare <512 x i1> @llvm.ppc.mma.xxsetaccz()
 declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)
 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
@@ -68,7 +68,7 @@
   %0 = load <16 x i8>, <16 x i8>* %Src, align 16
   %arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 1
   %1 = load <16 x i8>, <16 x i8>* %arrayidx1, align 16
-  %2 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %0, <16 x i8> %1)
+  %2 = tail call <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8> %0, <16 x i8> %1)
   %3 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
   %cmp11 = icmp sgt i32 %Len, 2
   br i1 %cmp11, label %for.body.preheader, label %for.cond.cleanup
@@ -165,7 +165,7 @@
   %0 = load <16 x i8>, <16 x i8>* %Src, align 16
   %arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 1
   %1 = load <16 x i8>, <16 x i8>* %arrayidx1, align 16
-  %2 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %0, <16 x i8> %1)
+  %2 = tail call <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8> %0, <16 x i8> %1)
   %arrayidx2 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 2
   %3 = load <16 x i8>, <16 x i8>* %arrayidx2, align 16
   %4 = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> %2, <16 x i8> %3)
Index: llvm/test/CodeGen/PowerPC/mma-outer-product.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/mma-outer-product.ll
+++ llvm/test/CodeGen/PowerPC/mma-outer-product.ll
@@ -6,8 +6,8 @@
 ; RUN:   -mcpu=pwr10 -ppc-track-subreg-liveness -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
 
-declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
-declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
+declare <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+declare <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8>, <16 x i8>)
 define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, i8* %ptr) {
 ; CHECK-LABEL: intrinsics1:
 ; CHECK:       # %bb.0:
@@ -56,11 +56,11 @@
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
-  %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc3, <16 x i8> %vc2, <16 x i8> %vc4)
+  %1 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> %vc1, <16 x i8> %vc3, <16 x i8> %vc2, <16 x i8> %vc4)
   %2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)
   %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
   %4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0)
-  %5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)
+  %5 = tail call <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8> %vc4, <16 x i8> %vc1)
   %6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1, i32 0, i32 0)
   %7 = bitcast i8* %ptr to <512 x i1>*
   store <512 x i1> %6, <512 x i1>* %7, align 64
@@ -120,11 +120,11 @@
   %vc2 = load <16 x i8>, <16 x i8>* %ptr2, align 16
   %vc3 = load <16 x i8>, <16 x i8>* %ptr3, align 16
   %vc4 = load <16 x i8>, <16 x i8>* %ptr4, align 16
-  %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4)
+  %1 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4)
   %2 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)
   %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
   %4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0)
-  %5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)
+  %5 = tail call <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8> %vc4, <16 x i8> %vc1)
   %6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1, i32 0, i32 0)
   %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %6)
   %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 0
Index: llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -7,7 +7,7 @@
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
 
 ; assemble_acc
-declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+declare <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 define void @ass_acc(<512 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_acc:
 ; CHECK:       # %bb.0: # %entry
@@ -35,7 +35,7 @@
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
-  %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
+  %0 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
   store <512 x i1> %0, <512 x i1>* %ptr, align 64
   ret void
 }
@@ -73,7 +73,7 @@
 entry:
 ; One xxmtacc is generated from the call to assemble.acc then one xxmtacc is
 ; generated from the call to xxmtacc then one xxmfacc is generated for the store
-  %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
+  %0 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
   %1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0)
   store <512 x i1> %1, <512 x i1>* %ptr, align 64
   ret void
@@ -110,7 +110,7 @@
 entry:
 ; One xxmtacc is generated from the call to assemble.acc then one xxmfacc is
 ; generated from the call to xxmfacc then one xxmfacc is generated for the store
-  %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
+  %0 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
   %1 = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> %0)
   store <512 x i1> %1, <512 x i1>* %ptr, align 64
   ret void
Index: llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
+++ llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
@@ -7,7 +7,7 @@
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
 
 declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
-declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+declare <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 declare void @foo()
 define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, i8* %ptr) {
 ; CHECK-LABEL: intrinsics1:
@@ -96,7 +96,7 @@
 ; CHECK-BE-NEXT:    ld r0, 16(r1)
 ; CHECK-BE-NEXT:    mtlr r0
 ; CHECK-BE-NEXT:    blr
-  %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4)
+  %1 = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4)
   %2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc3)
   tail call void @foo()
   %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1607,7 +1607,7 @@
 let Predicates = [MMA] in {
   def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
             (XXMTACC Concats.VecsToVecQuad)>;
-  def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
+  def : Pat<(v512i1 (int_ppc_mma_build_acc v16i8:$vs1, v16i8:$vs0,
                                               v16i8:$vs3, v16i8:$vs2)),
             (XXMTACC Concats.VecsToVecQuad)>;
   def : Pat<(v512i1 (PPCxxmfacc v512i1:$AS)), (XXMFACC acc:$AS)>;
@@ -1624,7 +1624,7 @@
 let Predicates = [PairedVectorMemops] in {
   def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)),
             Concats.VecsToVecPair0>;
-  def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)),
+  def : Pat<(v256i1 (int_ppc_vsx_build_pair v16i8:$vs1, v16i8:$vs0)),
             Concats.VecsToVecPair0>;
   def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)),
             (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1435,7 +1435,7 @@
 }
 
 let TargetPrefix = "ppc" in {
-  def int_ppc_vsx_assemble_pair :
+  def int_ppc_vsx_build_pair :
         Intrinsic<[llvm_v256i1_ty],
                   [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
 
@@ -1443,7 +1443,7 @@
         Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty],
                   [llvm_v256i1_ty], [IntrNoMem]>;
 
-  def int_ppc_mma_assemble_acc :
+  def int_ppc_mma_build_acc :
         Intrinsic<[llvm_v512i1_ty],
                   [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
                   [IntrNoMem]>;
Index: clang/test/SemaCXX/ppc-pair-mma-types.cpp
===================================================================
--- clang/test/SemaCXX/ppc-pair-mma-types.cpp
+++ clang/test/SemaCXX/ppc-pair-mma-types.cpp
@@ -367,7 +367,7 @@
     __vector_pair *vpp = (__vector_pair *)ptr;
     return *vpp; // expected-error {{invalid use of PPC MMA type}}
   };
-  auto f3 = [](vector unsigned char vc) { __vector_pair vp; __builtin_vsx_assemble_pair(&vp, vc, vc); return vp; }; // expected-error {{invalid use of PPC MMA type}}
+  auto f3 = [](vector unsigned char vc) { __vector_pair vp; __builtin_vsx_build_pair(&vp, vc, vc); return vp; }; // expected-error {{invalid use of PPC MMA type}}
 }
 
 // cast
Index: clang/test/Sema/ppc-pair-mma-types.c
===================================================================
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -246,7 +246,7 @@
   __vector_pair *vpp = (__vector_pair *)ptr;
   __vector_pair vp1 = *vpp;
   __vector_pair vp2;
-  __builtin_vsx_assemble_pair(&vp2, vc, vc);
+  __builtin_vsx_build_pair(&vp2, vc, vc);
   __vector_pair vp3;
   __vector_quad vq;
   __builtin_mma_xvf64ger(&vq, vp3, vc);
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===================================================================
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -3,7 +3,7 @@
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], <16 x i8> [[VC]], <16 x i8> [[VC]])
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.build.acc(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], <16 x i8> [[VC]], <16 x i8> [[VC]])
 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
 // CHECK-NEXT:    store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
 // CHECK-NEXT:    ret void
@@ -12,7 +12,7 @@
   __vector_quad vq = *((__vector_quad *)vqp);
   __vector_pair vp = *((__vector_pair *)vpp);
   __vector_quad res;
-  __builtin_mma_assemble_acc(&res, vc, vc, vc, vc);
+  __builtin_mma_build_acc(&res, vc, vc, vc, vc);
   *((__vector_quad *)resp) = res;
 }
 
@@ -44,7 +44,7 @@
 
 // CHECK-LABEL: @test3(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
 // CHECK-NEXT:    store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]]
 // CHECK-NEXT:    ret void
@@ -53,7 +53,7 @@
   __vector_quad vq = *((__vector_quad *)vqp);
   __vector_pair vp = *((__vector_pair *)vpp);
   __vector_pair res;
-  __builtin_vsx_assemble_pair(&res, vc, vc);
+  __builtin_vsx_build_pair(&res, vc, vc);
   *((__vector_pair *)resp) = res;
 }
 
@@ -1198,7 +1198,7 @@
 
 // CHECK-LABEL: @test76(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.build.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
 // CHECK-NEXT:    store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6]]
 // CHECK-NEXT:    ret void
Index: clang/include/clang/Basic/BuiltinsPPC.def
===================================================================
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -814,7 +814,7 @@
 // Provided builtins with _mma_ prefix for compatibility.
 CUSTOM_BUILTIN(mma_lxvp, vsx_lxvp, "W256SLLiW256C*", false)
 CUSTOM_BUILTIN(mma_stxvp, vsx_stxvp, "vW256SLLiW256C*", false)
-CUSTOM_BUILTIN(mma_assemble_pair, vsx_assemble_pair, "vW256*VV", false)
+CUSTOM_BUILTIN(mma_assemble_pair, vsx_build_pair, "vW256*VV", false)
 CUSTOM_BUILTIN(mma_disassemble_pair, vsx_disassemble_pair, "vv*W256*", false)
 
 // UNALIASED_CUSTOM_BUILTIN macro is used for built-ins that have
@@ -824,10 +824,10 @@
 
 UNALIASED_CUSTOM_BUILTIN(vsx_lxvp, "W256SLLiW256C*", false)
 UNALIASED_CUSTOM_BUILTIN(vsx_stxvp, "vW256SLLiW256C*", false)
-UNALIASED_CUSTOM_BUILTIN(vsx_assemble_pair, "vW256*VV", false)
+UNALIASED_CUSTOM_BUILTIN(vsx_build_pair, "vW256*VV", false)
 UNALIASED_CUSTOM_BUILTIN(vsx_disassemble_pair, "vv*W256*", false)
 
-UNALIASED_CUSTOM_BUILTIN(mma_assemble_acc, "vW512*VVVV", false)
+UNALIASED_CUSTOM_BUILTIN(mma_build_acc, "vW512*VVVV", false)
 UNALIASED_CUSTOM_BUILTIN(mma_disassemble_acc, "vv*W512*", false)
 UNALIASED_CUSTOM_BUILTIN(mma_xxmtacc, "vW512*", true)
 UNALIASED_CUSTOM_BUILTIN(mma_xxmfacc, "vW512*", true)

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