pengfei added a comment. In D107082#2913881 <https://reviews.llvm.org/D107082#2913881>, @craig.topper wrote:
> I haven't had a chance to look at this patch in detail, but I wanted to ask > if you considered doing what ARM and RISCV do for this. They pass the f16 in > the lower bits on an f32 by only changing the ABI handling code in the > backend. The type legalizer takes care of the rest. That seems simpler than > this patch. See for example https://reviews.llvm.org/D98670 Thanks Craig for the information. I referenced implementation in AArch64. I think we have to add a legal f16 type in this way because: 1. We will support `_Float16` type in Clang on SSE2 and above to keep the same behavior with GCC. So a legal type is a must. 2. Using lower 16bits of f32 may not satisfice the requirment from calling conversion of aggregation type and complex type defined by psABI. 3. We have some optimizations to leverage F16C or AVX512 ps2ph/ph2ps instructions. A legal type is easy to customize. Besides, we have full arithmatic f16 support in AVX512FP16. Most of the code here are shared and served for both scenarios. We just need to promote for most FP operations and expand or customize `FP_ROUND` and `FP_EXTEND` here. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107082/new/ https://reviews.llvm.org/D107082 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
