HsiangKai created this revision.
HsiangKai added reviewers: frasercrmck, khchen, arcbbb, rogfer01, evandro,
craig.topper.
Herald added subscribers: StephenFan, vkmr, luismarques, apazos,
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,
brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng,
niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added projects: clang, LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D106939
Files:
clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
Index: llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+
+declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ <vscale x 8 x i8>,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i8> @intrinsic_vadd_maskedoff_undef(<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_maskedoff_undef:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> %0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i1> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i8> %a
+}
Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -376,17 +376,27 @@
// over the tail values. Some pseudo instructions force a tail agnostic
policy
// despite having a tied def.
bool ForceTailAgnostic = RISCVII::doesForceTailAgnostic(TSFlags);
+ // hasDummyMaskOp(TSFlags) == ture means it is a non-masked instruction.
+ // FIXME: hasDummyMaskOp() is the closest attribute to distinguish masked
+ // and non-masked instructions. However, there are some exceptions for this
+ // attribute. PseudoVMV_V_[VXI] and PseudoVFMV_V_F have no need to append
+ // the dummy mask operand in MC lowering and they are non-masked
instructions.
+ bool MaskAgnostic = RISCVII::hasDummyMaskOp(TSFlags) ? true : false;
bool TailAgnostic = true;
unsigned UseOpIdx;
- if (!ForceTailAgnostic && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
- TailAgnostic = false;
- // If the tied operand is an IMPLICIT_DEF we can keep TailAgnostic.
+ if (MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
+ if (!ForceTailAgnostic)
+ TailAgnostic = false;
+ // If the tied operand is an IMPLICIT_DEF we can keep MaskAgnostic and
+ // TailAgnostic.
const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
MachineInstr *UseMI = MRI->getVRegDef(UseMO.getReg());
if (UseMI) {
UseMI = elideCopies(UseMI, MRI);
- if (UseMI && UseMI->isImplicitDef())
+ if (UseMI && UseMI->isImplicitDef()) {
+ MaskAgnostic = true;
TailAgnostic = true;
+ }
}
}
@@ -399,7 +409,7 @@
} else
InstrInfo.setAVLReg(RISCV::NoRegister);
InstrInfo.setVTYPE(VLMul, SEW, /*TailAgnostic*/ TailAgnostic,
- /*MaskAgnostic*/ false, MaskRegOp);
+ /*MaskAgnostic*/ MaskAgnostic, MaskRegOp);
return InstrInfo;
}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
@@ -0,0 +1,16 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg \
+// RUN: | FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8m1_m(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8>
@llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x
i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]],
i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vadd_vv_i8m1_m (vbool8_t mask, vint8m1_t op1, vint8m1_t op2,
size_t vl) {
+ return vadd_vv_i8m1_m(mask, vundefined_i8m1(), op1, op2, vl);
+}
Index: llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+
+declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ <vscale x 8 x i8>,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i8> @intrinsic_vadd_maskedoff_undef(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_maskedoff_undef:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> %0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i1> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i8> %a
+}
Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -376,17 +376,27 @@
// over the tail values. Some pseudo instructions force a tail agnostic policy
// despite having a tied def.
bool ForceTailAgnostic = RISCVII::doesForceTailAgnostic(TSFlags);
+ // hasDummyMaskOp(TSFlags) == ture means it is a non-masked instruction.
+ // FIXME: hasDummyMaskOp() is the closest attribute to distinguish masked
+ // and non-masked instructions. However, there are some exceptions for this
+ // attribute. PseudoVMV_V_[VXI] and PseudoVFMV_V_F have no need to append
+ // the dummy mask operand in MC lowering and they are non-masked instructions.
+ bool MaskAgnostic = RISCVII::hasDummyMaskOp(TSFlags) ? true : false;
bool TailAgnostic = true;
unsigned UseOpIdx;
- if (!ForceTailAgnostic && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
- TailAgnostic = false;
- // If the tied operand is an IMPLICIT_DEF we can keep TailAgnostic.
+ if (MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
+ if (!ForceTailAgnostic)
+ TailAgnostic = false;
+ // If the tied operand is an IMPLICIT_DEF we can keep MaskAgnostic and
+ // TailAgnostic.
const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
MachineInstr *UseMI = MRI->getVRegDef(UseMO.getReg());
if (UseMI) {
UseMI = elideCopies(UseMI, MRI);
- if (UseMI && UseMI->isImplicitDef())
+ if (UseMI && UseMI->isImplicitDef()) {
+ MaskAgnostic = true;
TailAgnostic = true;
+ }
}
}
@@ -399,7 +409,7 @@
} else
InstrInfo.setAVLReg(RISCV::NoRegister);
InstrInfo.setVTYPE(VLMul, SEW, /*TailAgnostic*/ TailAgnostic,
- /*MaskAgnostic*/ false, MaskRegOp);
+ /*MaskAgnostic*/ MaskAgnostic, MaskRegOp);
return InstrInfo;
}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/maskedoff-undefined.c
@@ -0,0 +1,16 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg \
+// RUN: | FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8m1_m(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vadd_vv_i8m1_m (vbool8_t mask, vint8m1_t op1, vint8m1_t op2, size_t vl) {
+ return vadd_vv_i8m1_m(mask, vundefined_i8m1(), op1, op2, vl);
+}
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