khchen updated this revision to Diff 361216.
khchen added a comment.
address arichardson's comment, thanks!
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105555/new/
https://reviews.llvm.org/D105555
Files:
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/CodeGen/RISCV/riscv-metadata.c
llvm/include/llvm/Support/TargetParser.h
llvm/lib/Support/TargetParser.cpp
Index: llvm/lib/Support/TargetParser.cpp
===================================================================
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -331,5 +331,20 @@
return true;
}
+StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo,
+ bool Is64Bit) {
+ bool HasD = ISAInfo.hasExtension("d");
+ if (!Is64Bit) {
+ if (HasD)
+ return "ilp32d";
+ if (ISAInfo.hasExtension("e"))
+ return "ilp32e";
+ return "ilp32";
+ }
+ if (HasD)
+ return "lp64d";
+ return "lp64";
+}
+
} // namespace RISCV
} // namespace llvm
Index: llvm/include/llvm/Support/TargetParser.h
===================================================================
--- llvm/include/llvm/Support/TargetParser.h
+++ llvm/include/llvm/Support/TargetParser.h
@@ -17,8 +17,9 @@
// FIXME: vector is used because that's what clang uses for subtarget feature
// lists, but SmallVector would probably be better
#include "llvm/ADT/Triple.h"
-#include "llvm/Support/ARMTargetParser.h"
#include "llvm/Support/AArch64TargetParser.h"
+#include "llvm/Support/ARMTargetParser.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include <vector>
namespace llvm {
@@ -174,6 +175,8 @@
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector<StringRef> &Features);
StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
+StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo,
+ bool IsRV64);
} // namespace RISCV
Index: clang/test/CodeGen/RISCV/riscv-metadata.c
===================================================================
--- clang/test/CodeGen/RISCV/riscv-metadata.c
+++ clang/test/CodeGen/RISCV/riscv-metadata.c
@@ -1,14 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-ILP32 %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -o - %s | FileCheck -check-prefix=EMPTY-ILP32D %s
// RUN: %clang_cc1 -triple riscv32 -target-abi ilp32 -emit-llvm -o - %s | FileCheck -check-prefix=ILP32 %s
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm -o - %s | FileCheck -check-prefix=ILP32F %s
// RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-abi ilp32d -emit-llvm -o - %s | FileCheck -check-prefix=ILP32D %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64D %s
// RUN: %clang_cc1 -triple riscv64 -target-abi lp64 -emit-llvm -o - %s | FileCheck -check-prefix=LP64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-abi lp64f -emit-llvm -o - %s | FileCheck -check-prefix=LP64F %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +d -target-abi lp64d -emit-llvm -o - %s | FileCheck -check-prefix=LP64D %s
+// Test expected behavior when giving -target-cpu
+// This cc1 test is similar to clang with -march=rv32ifd -mcpu=sifive-e31, default abi is ilp32d
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -target-cpu sifive-e31 -o - %s | FileCheck -check-prefix=EMPTY-ILP32D %s
+// This cc1 test is similar to clang with -march=rv64i -mcpu=sifive-u74, default abi is lp64
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - -target-cpu sifive-u74 %s | FileCheck -check-prefix=EMPTY-LP64 %s
+
+// EMPTY-ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
+// EMPTY-ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
// ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
// ILP32F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32f"}
// ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
+// EMPTY-LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
+// EMPTY-LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}
// LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
// LP64F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64f"}
// LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===================================================================
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -197,22 +197,9 @@
// Ignore parsing error, just go 3rd step.
consumeError(std::move(E));
} else {
- bool HasD = ISAInfo.hasExtension("d");
unsigned XLen = ISAInfo.getXLen();
- if (XLen == 32) {
- bool HasE = ISAInfo.hasExtension("e");
- if (HasD)
- return "ilp32d";
- else if (HasE)
- return "ilp32e";
- else
- return "ilp32";
- } else if (XLen == 64) {
- if (HasD)
- return "lp64d";
- else
- return "lp64";
- }
+ return llvm::RISCV::computeDefaultABIFromArch(ISAInfo,
+ /*IsRV64=*/XLen == 64);
}
// 3. Choose a default based on the triple
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -229,6 +229,12 @@
unsigned XLen = getTriple().isArch64Bit() ? 64 : 32;
ISAInfo.parse(XLen, Features);
+ // Use the explicitly target-feature to compute default ABI.
+ if (getABI().empty()) {
+ bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
+ ABI = llvm::RISCV::computeDefaultABIFromArch(ISAInfo, Is64Bit).str();
+ }
+
return true;
}
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