nemanjai added inline comments.
================ Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:831 +// 64bit version of popcntb for 64bit sized unsigned long. +let isCodeGenOnly = 1 in +def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), ---------------- efriedma wrote: > I'm sort of confused by the instruction variations here... let me see if I'm > understanding correctly: > > 1. popcntb always produces a 64-bit result. > 2. The 32-bit variation of the intrinsic just throws away the high bits. > 3. We can't use the 64-bit instruction in "32-bit" mode because we marked the > register class illegal in isel, and Feature64BitRegs has been marked "beta" > for the last 15 years. > 4. Therefore, there are two versions of the instruction: the real instruction > that produces a 64-bit result, and a fake version of the instruction we can > use in 32-bit mode. This is correct. We have two GPR register classes that model the same register file. The `gprc` registers pretend the high bits don't exist. The two versions of the instructions that have GPR operands are quite common in PPC. There have historically been some operating systems on which context switches spill the full width GPRs even in 32-bit mode. Others spill only the low 32 bits of the GPRs. The addition of two different register classes and `Feature64BitRegs` likely had to do with that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105360/new/ https://reviews.llvm.org/D105360 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
