Conanap added inline comments.
================
Comment at:
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll:18
entry:
- %0 = bitcast i64* %a to i8*
- %1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
- ret i64 %1
+ %0 = call i64 asm sideeffect "ldarx $0, $1", "=r,*Z,~{memory}"(i64* %a)
+ ret i64 %0
----------------
nemanjai wrote:
> Conanap wrote:
> > nemanjai wrote:
> > > This is not the asm that the front end generates. Why would you generate
> > > one thing in the front end and then test a different thing in the back
> > > end?
> > I'm not quite sure what you mean by this; the IR output is taken from the
> > `.c` test case above.
> I don't think that is the case.
> Above:
> `call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* %a)`
> Here:
> `call i64 asm sideeffect "ldarx $0, $1", "=r,*Z,~{memory}"(i64* %a)`
ah I see I missed the modifier.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105754/new/
https://reviews.llvm.org/D105754
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