nemanjai requested changes to this revision. nemanjai added inline comments. This revision now requires changes to proceed.
================ Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1733 +// as XL produces a tweq <regA>, <regA>. +def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 31), + (TD 4, $A, $B)>; ---------------- This is supposed to be an unconditional trap and the produced sequence is not that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103668/new/ https://reviews.llvm.org/D103668 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
