HsiangKai created this revision. HsiangKai added reviewers: khchen, arcbbb. Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb. HsiangKai requested review of this revision. Herald added subscribers: cfe-commits, MaskRay. Herald added a project: clang.
We have vector operations on double vector and float scalar. For example, vfwadd.wf is such a instruction. vfloat64m1_t vfwadd_wf(vfloat64m1_t op0, float op1, size_t op2); We should specify F and D extensions for it. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D102051 Files: clang/utils/TableGen/RISCVVEmitter.cpp Index: clang/utils/TableGen/RISCVVEmitter.cpp =================================================================== --- clang/utils/TableGen/RISCVVEmitter.cpp +++ clang/utils/TableGen/RISCVVEmitter.cpp @@ -107,6 +107,9 @@ bool isFloatVector(unsigned Width) const { return isVector() && isFloat() && ElementBitwidth == Width; } + bool isFloat(unsigned Width) const { + return isFloat() && ElementBitwidth == Width; + } private: // Verify RVV vector type and set Valid. @@ -765,11 +768,11 @@ } // Init RISC-V extensions for (const auto &T : OutInTypes) { - if (T->isFloatVector(16)) + if (T->isFloatVector(16) || T->isFloat(16)) RISCVExtensions |= RISCVExtension::Zfh; - else if (T->isFloatVector(32)) + else if (T->isFloatVector(32) || T->isFloat(32)) RISCVExtensions |= RISCVExtension::F; - else if (T->isFloatVector(64)) + else if (T->isFloatVector(64) || T->isFloat(64)) RISCVExtensions |= RISCVExtension::D; } if (RequiredExtension == "Zvamo")
Index: clang/utils/TableGen/RISCVVEmitter.cpp =================================================================== --- clang/utils/TableGen/RISCVVEmitter.cpp +++ clang/utils/TableGen/RISCVVEmitter.cpp @@ -107,6 +107,9 @@ bool isFloatVector(unsigned Width) const { return isVector() && isFloat() && ElementBitwidth == Width; } + bool isFloat(unsigned Width) const { + return isFloat() && ElementBitwidth == Width; + } private: // Verify RVV vector type and set Valid. @@ -765,11 +768,11 @@ } // Init RISC-V extensions for (const auto &T : OutInTypes) { - if (T->isFloatVector(16)) + if (T->isFloatVector(16) || T->isFloat(16)) RISCVExtensions |= RISCVExtension::Zfh; - else if (T->isFloatVector(32)) + else if (T->isFloatVector(32) || T->isFloat(32)) RISCVExtensions |= RISCVExtension::F; - else if (T->isFloatVector(64)) + else if (T->isFloatVector(64) || T->isFloat(64)) RISCVExtensions |= RISCVExtension::D; } if (RequiredExtension == "Zvamo")
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