[PATCH] D98457: [WebAssembly] Remove unimplemented-simd target features

Thomas Lively via Phabricator via cfe-commits Thu, 11 Mar 2021 14:46:51 -0800

tlively created this revision.
tlively added reviewers: aheejin, dschuff.
Herald added subscribers: jansvoboda11, wingo, dang, ecnelises, jfb, arphaman, 
sunfish, hiraditya, jgravelle-google, sbc100.
tlively requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.


Now that the WebAssembly SIMD specification is finalized and engines are
generally up-to-date, there is no need for a separate target feature for gating
SIMD instructions that engines have not implemented. With this change,
v128.const is now enabled by default with the simd128 target feature.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98457

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  clang/test/Preprocessor/wasm-target-features.c
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/test/CodeGen/WebAssembly/simd-arith.ll
  llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
  llvm/test/CodeGen/WebAssembly/simd-comparisons.ll
  llvm/test/CodeGen/WebAssembly/simd-conversions.ll
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
  llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
  llvm/test/CodeGen/WebAssembly/simd-noopt.ll
  llvm/test/CodeGen/WebAssembly/simd-reductions.ll
  llvm/test/CodeGen/WebAssembly/simd-select.ll
  llvm/test/CodeGen/WebAssembly/simd-sext-inreg.ll
  llvm/test/CodeGen/WebAssembly/simd-unsupported.ll
  llvm/test/CodeGen/WebAssembly/simd.ll
  llvm/test/MC/WebAssembly/basic-assembly.s
  llvm/test/MC/WebAssembly/data-section.s
  llvm/test/MC/WebAssembly/simd-encodings.s
  llvm/test/MC/WebAssembly/type-index.s
  llvm/test/MC/WebAssembly/types.ll
  llvm/test/MC/WebAssembly/wasm64.s

Index: llvm/test/MC/WebAssembly/wasm64.s
===================================================================
--- llvm/test/MC/WebAssembly/wasm64.s
+++ llvm/test/MC/WebAssembly/wasm64.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -triple=wasm64-unknown-unknown -mattr=+atomics,+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
-# RUN: llvm-mc -triple=wasm64-unknown-unknown -filetype=obj -mattr=+atomics,+unimplemented-simd128,+nontrapping-fptoint,+exception-handling -o - < %s | obj2yaml | FileCheck %s -check-prefix=BIN
+# RUN: llvm-mc -triple=wasm64-unknown-unknown -mattr=+atomics,+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
+# RUN: llvm-mc -triple=wasm64-unknown-unknown -filetype=obj -mattr=+atomics,+simd128,+nontrapping-fptoint,+exception-handling -o - < %s | obj2yaml | FileCheck %s -check-prefix=BIN
 
 # Most of our other tests are for wasm32, this one adds some wasm64 specific tests.
 
Index: llvm/test/MC/WebAssembly/types.ll
===================================================================
--- llvm/test/MC/WebAssembly/types.ll
+++ llvm/test/MC/WebAssembly/types.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=+unimplemented-simd128 -filetype=obj %s -o - | obj2yaml | FileCheck %s
+; RUN: llc -mattr=+simd128 -filetype=obj %s -o - | obj2yaml | FileCheck %s
 
 target triple = "wasm32-unknown-unknown"
 
Index: llvm/test/MC/WebAssembly/type-index.s
===================================================================
--- llvm/test/MC/WebAssembly/type-index.s
+++ llvm/test/MC/WebAssembly/type-index.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
 # Check that it converts to .o without errors:
-# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefix=BIN %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefix=BIN %s
 
 # Minimal test for type indices in call_indirect.
 
Index: llvm/test/MC/WebAssembly/simd-encodings.s
===================================================================
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -show-encoding -triple=wasm32-unknown-unknown -mattr=+unimplemented-simd128 < %s | FileCheck %s
+# RUN: llvm-mc -show-encoding -triple=wasm32-unknown-unknown -mattr=+simd128 < %s | FileCheck %s
 
 main:
     .functype main () -> ()
Index: llvm/test/MC/WebAssembly/data-section.s
===================================================================
--- llvm/test/MC/WebAssembly/data-section.s
+++ llvm/test/MC/WebAssembly/data-section.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
 # Check that it converts to .o without errors:
-# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefixes=BIN,BIN32 %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefixes=BIN,BIN32 %s
 
 # Same again for wasm64
 
-# RUN: llvm-mc -triple=wasm64-unknown-unknown -mattr=+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
+# RUN: llvm-mc -triple=wasm64-unknown-unknown -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
 # Check that it converts to .o without errors:
-# RUN: llvm-mc -triple=wasm64-unknown-unknown -filetype=obj -mattr=+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefixes=BIN,BIN64 %s
+# RUN: llvm-mc -triple=wasm64-unknown-unknown -filetype=obj -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefixes=BIN,BIN64 %s
 
 # Minimal test for data sections.
 
Index: llvm/test/MC/WebAssembly/basic-assembly.s
===================================================================
--- llvm/test/MC/WebAssembly/basic-assembly.s
+++ llvm/test/MC/WebAssembly/basic-assembly.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+atomics,+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+atomics,+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
 # Check that it converts to .o without errors, but don't check any output:
-# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+atomics,+unimplemented-simd128,+nontrapping-fptoint,+exception-handling -o %t.o < %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+atomics,+simd128,+nontrapping-fptoint,+exception-handling -o %t.o < %s
 
 
 empty_func:
Index: llvm/test/CodeGen/WebAssembly/simd.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd.ll
+++ llvm/test/CodeGen/WebAssembly/simd.ll
@@ -1,5 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that basic SIMD128 vector manipulation operations assemble as expected.
@@ -12,7 +11,6 @@
 ; ==============================================================================
 ; CHECK-LABEL: const_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v16i8 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=,
 ; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
@@ -277,7 +275,6 @@
 ; ==============================================================================
 ; CHECK-LABEL: const_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v8i16 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 256, 770, 1284, 1798, 2312, 2826, 3340, 3854{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -526,7 +523,6 @@
 ; ==============================================================================
 ; CHECK-LABEL: const_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v4i32 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 50462976, 117835012, 185207048, 252579084{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -678,7 +674,6 @@
 ; ==============================================================================
 ; CHECK-LABEL: const_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v2i64 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 506097522914230528, 1084818905618843912{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -824,7 +819,6 @@
 ; ==============================================================================
 ; CHECK-LABEL: const_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v4f32 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=,
 ; SIMD128-SAME: 0x1.0402p-121, 0x1.0c0a08p-113, 0x1.14121p-105, 0x1.1c1a18p-97{{$}}
@@ -978,7 +972,6 @@
 ; ==============================================================================
 ; CHECK-LABEL: const_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v2f64 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
Index: llvm/test/CodeGen/WebAssembly/simd-unsupported.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-unsupported.ll
+++ llvm/test/CodeGen/WebAssembly/simd-unsupported.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
 
 ; Test that operations that are not supported by SIMD are properly
 ; unrolled.
Index: llvm/test/CodeGen/WebAssembly/simd-sext-inreg.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-sext-inreg.ll
+++ llvm/test/CodeGen/WebAssembly/simd-sext-inreg.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that vector sign extensions lower to shifts
Index: llvm/test/CodeGen/WebAssembly/simd-select.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-select.ll
+++ llvm/test/CodeGen/WebAssembly/simd-select.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mattr=+unimplemented-simd128 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mattr=+simd128 | FileCheck %s
 
 ; Test that vector selects of various varieties lower correctly.
 
Index: llvm/test/CodeGen/WebAssembly/simd-reductions.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-reductions.ll
+++ llvm/test/CodeGen/WebAssembly/simd-reductions.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
 
 ; Tests that redundant masking and conversions are folded out
 ; following SIMD reduction instructions.
@@ -13,9 +13,9 @@
 declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>)
 
 ; CHECK-LABEL: any_v16i8_trunc:
-; SIMD128-NEXT: .functype any_v16i8_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v16i8_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v16i8_trunc(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   %b = trunc i32 %a to i1
@@ -24,9 +24,9 @@
 }
 
 ; CHECK-LABEL: any_v16i8_ne:
-; SIMD128-NEXT: .functype any_v16i8_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v16i8_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v16i8_ne(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   %b = icmp ne i32 %a, 0
@@ -35,9 +35,9 @@
 }
 
 ; CHECK-LABEL: any_v16i8_eq:
-; SIMD128-NEXT: .functype any_v16i8_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v16i8_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v16i8_eq(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   %b = icmp eq i32 %a, 1
@@ -46,9 +46,9 @@
 }
 
 ; CHECK-LABEL: all_v16i8_trunc:
-; SIMD128-NEXT: .functype all_v16i8_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v16i8_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v16i8_trunc(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)
   %b = trunc i32 %a to i1
@@ -57,9 +57,9 @@
 }
 
 ; CHECK-LABEL: all_v16i8_ne:
-; SIMD128-NEXT: .functype all_v16i8_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v16i8_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v16i8_ne(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)
   %b = icmp ne i32 %a, 0
@@ -68,9 +68,9 @@
 }
 
 ; CHECK-LABEL: all_v16i8_eq:
-; SIMD128-NEXT: .functype all_v16i8_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v16i8_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v16i8_eq(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)
   %b = icmp eq i32 %a, 1
@@ -85,9 +85,9 @@
 declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>)
 
 ; CHECK-LABEL: any_v8i16_trunc:
-; SIMD128-NEXT: .functype any_v8i16_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v8i16_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v8i16_trunc(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   %b = trunc i32 %a to i1
@@ -96,9 +96,9 @@
 }
 
 ; CHECK-LABEL: any_v8i16_ne:
-; SIMD128-NEXT: .functype any_v8i16_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v8i16_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v8i16_ne(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   %b = icmp ne i32 %a, 0
@@ -107,9 +107,9 @@
 }
 
 ; CHECK-LABEL: any_v8i16_eq:
-; SIMD128-NEXT: .functype any_v8i16_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v8i16_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v8i16_eq(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   %b = icmp eq i32 %a, 1
@@ -118,9 +118,9 @@
 }
 
 ; CHECK-LABEL: all_v8i16_trunc:
-; SIMD128-NEXT: .functype all_v8i16_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v8i16_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v8i16_trunc(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
   %b = trunc i32 %a to i1
@@ -129,9 +129,9 @@
 }
 
 ; CHECK-LABEL: all_v8i16_ne:
-; SIMD128-NEXT: .functype all_v8i16_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v8i16_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v8i16_ne(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
   %b = icmp ne i32 %a, 0
@@ -140,9 +140,9 @@
 }
 
 ; CHECK-LABEL: all_v8i16_eq:
-; SIMD128-NEXT: .functype all_v8i16_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v8i16_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v8i16_eq(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
   %b = icmp eq i32 %a, 1
@@ -157,9 +157,9 @@
 declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>)
 
 ; CHECK-LABEL: any_v4i32_trunc:
-; SIMD128-NEXT: .functype any_v4i32_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v4i32_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v4i32_trunc(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   %b = trunc i32 %a to i1
@@ -168,9 +168,9 @@
 }
 
 ; CHECK-LABEL: any_v4i32_ne:
-; SIMD128-NEXT: .functype any_v4i32_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v4i32_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v4i32_ne(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   %b = icmp ne i32 %a, 0
@@ -179,9 +179,9 @@
 }
 
 ; CHECK-LABEL: any_v4i32_eq:
-; SIMD128-NEXT: .functype any_v4i32_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v4i32_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v4i32_eq(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   %b = icmp eq i32 %a, 1
@@ -190,9 +190,9 @@
 }
 
 ; CHECK-LABEL: all_v4i32_trunc:
-; SIMD128-NEXT: .functype all_v4i32_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v4i32_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v4i32_trunc(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)
   %b = trunc i32 %a to i1
@@ -201,9 +201,9 @@
 }
 
 ; CHECK-LABEL: all_v4i32_ne:
-; SIMD128-NEXT: .functype all_v4i32_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v4i32_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v4i32_ne(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)
   %b = icmp ne i32 %a, 0
@@ -212,9 +212,9 @@
 }
 
 ; CHECK-LABEL: all_v4i32_eq:
-; SIMD128-NEXT: .functype all_v4i32_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v4i32_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v4i32_eq(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)
   %b = icmp eq i32 %a, 1
@@ -229,9 +229,9 @@
 declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>)
 
 ; CHECK-LABEL: any_v2i64_trunc:
-; SIMD128-NEXT: .functype any_v2i64_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v2i64_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v2i64_trunc(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   %b = trunc i32 %a to i1
@@ -240,9 +240,9 @@
 }
 
 ; CHECK-LABEL: any_v2i64_ne:
-; SIMD128-NEXT: .functype any_v2i64_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v2i64_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v2i64_ne(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   %b = icmp ne i32 %a, 0
@@ -251,9 +251,9 @@
 }
 
 ; CHECK-LABEL: any_v2i64_eq:
-; SIMD128-NEXT: .functype any_v2i64_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v2i64_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v2i64_eq(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   %b = icmp eq i32 %a, 1
@@ -262,9 +262,9 @@
 }
 
 ; CHECK-LABEL: all_v2i64_trunc:
-; SIMD128-NEXT: .functype all_v2i64_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v2i64_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v2i64_trunc(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
   %b = trunc i32 %a to i1
@@ -273,9 +273,9 @@
 }
 
 ; CHECK-LABEL: all_v2i64_ne:
-; SIMD128-NEXT: .functype all_v2i64_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v2i64_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v2i64_ne(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
   %b = icmp ne i32 %a, 0
@@ -284,9 +284,9 @@
 }
 
 ; CHECK-LABEL: all_v2i64_eq:
-; SIMD128-NEXT: .functype all_v2i64_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v2i64_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v2i64_eq(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
   %b = icmp eq i32 %a, 1
Index: llvm/test/CodeGen/WebAssembly/simd-noopt.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-noopt.ll
+++ /dev/null
@@ -1,20 +0,0 @@
-; RUN: llc < %s -fast-isel -mattr=+simd128,+sign-ext -verify-machineinstrs
-
-;; Ensures fastisel produces valid code when storing and loading split
-;; up v2i64 values. Lowering away v2i64s is a temporary measure while
-;; V8 does not have support for i64x2.* operations, and is done when
-;; -wasm-enable-unimplemented-simd is not present. This is a
-;; regression test for a bug that crashed llc after fastisel produced
-;; machineinstrs that used registers that had never been defined.
-
-target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
-target triple = "wasm32-unknown-unknown"
-
-define i64 @foo(<2 x i64> %vec) {
-entry:
-  %vec.addr = alloca <2 x i64>, align 16
-  store <2 x i64> %vec, <2 x i64>* %vec.addr, align 16
-  %0 = load <2 x i64>, <2 x i64>* %vec.addr, align 16
-  %1 = extractelement <2 x i64> %0, i32 0
-  ret i64 %1
-}
Index: llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
+++ llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
 
 ; Test loads and stores with custom alignment values.
 
Index: llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
+++ llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s
 
 ; Regression test for an ISel failure when a splatted load had more
 ; than one use. The main tests for load_splat are in simd-offset.ll.
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s
 
 ; Test that SIMD128 intrinsics lower as expected. These intrinsics are
 ; only expected to lower successfully if the simd128 attribute is
@@ -12,9 +12,9 @@
 ; 16 x i8
 ; ==============================================================================
 ; CHECK-LABEL: swizzle_v16i8:
-; SIMD128-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>)
 define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y)
@@ -22,9 +22,9 @@
 }
 
 ; CHECK-LABEL: add_sat_s_v16i8:
-; SIMD128-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
@@ -32,9 +32,9 @@
 }
 
 ; CHECK-LABEL: add_sat_u_v16i8:
-; SIMD128-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
@@ -42,9 +42,9 @@
 }
 
 ; CHECK-LABEL: sub_sat_s_v16i8:
-; SIMD128-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(
@@ -54,9 +54,9 @@
 }
 
 ; CHECK-LABEL: sub_sat_u_v16i8:
-; SIMD128-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(
@@ -66,9 +66,9 @@
 }
 
 ; CHECK-LABEL: avgr_u_v16i8:
-; SIMD128-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y)
@@ -76,9 +76,9 @@
 }
 
 ; CHECK-LABEL: popcnt_v16i8:
-; SIMD128-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.popcnt(<16 x i8>)
 define <16 x i8> @popcnt_v16i8(<16 x i8> %x) {
  %a = call <16 x i8> @llvm.wasm.popcnt(<16 x i8> %x)
@@ -86,9 +86,9 @@
 }
 
 ; CHECK-LABEL: any_v16i8:
-; SIMD128-NEXT: .functype any_v16i8 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v16i8 (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>)
 define i32 @any_v16i8(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
@@ -96,9 +96,9 @@
 }
 
 ; CHECK-LABEL: all_v16i8:
-; SIMD128-NEXT: .functype all_v16i8 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v16i8 (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>)
 define i32 @all_v16i8(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)
@@ -106,9 +106,9 @@
 }
 
 ; CHECK-LABEL: bitmask_v16i8:
-; SIMD128-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>)
 define i32 @bitmask_v16i8(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x)
@@ -116,9 +116,9 @@
 }
 
 ; CHECK-LABEL: bitselect_v16i8:
-; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
 define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) {
   %a = call <16 x i8> @llvm.wasm.bitselect.v16i8(
@@ -128,9 +128,9 @@
 }
 
 ; CHECK-LABEL: signselect_v16i8:
-; SIMD128-NEXT: .functype signselect_v16i8 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype signselect_v16i8 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.signselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
 define <16 x i8> @signselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) {
   %a = call <16 x i8> @llvm.wasm.signselect.v16i8(
@@ -140,9 +140,9 @@
 }
 
 ; CHECK-LABEL: narrow_signed_v16i8:
-; SIMD128-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>)
 define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) {
   %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(
@@ -152,9 +152,9 @@
 }
 
 ; CHECK-LABEL: narrow_unsigned_v16i8:
-; SIMD128-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>)
 define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) {
   %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(
@@ -164,11 +164,11 @@
 }
 
 ; CHECK-LABEL: shuffle_v16i8:
-; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
-; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; NO-CHECK-NOT: i8x16
+; CHECK-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.shuffle(
   <16 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
   i32, i32, i32, i32, i32)
@@ -180,11 +180,11 @@
 }
 
 ; CHECK-LABEL: shuffle_undef_v16i8:
-; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
-; SIMD128-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; NO-CHECK-NOT: i8x16
+; CHECK-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; CHECK-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y,
       i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,
@@ -197,9 +197,9 @@
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: add_sat_s_v8i16:
-; SIMD128-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
@@ -207,9 +207,9 @@
 }
 
 ; CHECK-LABEL: add_sat_u_v8i16:
-; SIMD128-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
@@ -217,9 +217,9 @@
 }
 
 ; CHECK-LABEL: sub_sat_s_v8i16:
-; SIMD128-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(
@@ -229,9 +229,9 @@
 }
 
 ; CHECK-LABEL: sub_sat_u_v8i16:
-; SIMD128-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(
@@ -241,9 +241,9 @@
 }
 
 ; CHECK-LABEL: avgr_u_v8i16:
-; SIMD128-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y)
@@ -251,9 +251,9 @@
 }
 
 ; CHECK-LABEL: q15mulr_sat_s_v8i16:
-; SIMD128-NEXT: .functype q15mulr_sat_s_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.q15mulr_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype q15mulr_sat_s_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.q15mulr_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.q15mulr.saturate.signed(<8 x i16>, <8 x i16>)
 define <8 x i16> @q15mulr_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.wasm.q15mulr.saturate.signed(<8 x i16> %x,
@@ -262,9 +262,9 @@
 }
 
 ; CHECK-LABEL: extmul_low_s_v8i16:
-; SIMD128-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extmul.low.signed.v8i16(<16 x i8>, <16 x i8>)
 define <8 x i16> @extmul_low_s_v8i16(<16 x i8> %x, <16 x i8> %y) {
   %a = call <8 x i16> @llvm.wasm.extmul.low.signed.v8i16(
@@ -274,9 +274,9 @@
 }
 
 ; CHECK-LABEL: extmul_high_s_v8i16:
-; SIMD128-NEXT: .functype extmul_high_s_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extmul_high_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_s_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extmul_high_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extmul.high.signed.v8i16(<16 x i8>, <16 x i8>)
 define <8 x i16> @extmul_high_s_v8i16(<16 x i8> %x, <16 x i8> %y) {
   %a = call <8 x i16> @llvm.wasm.extmul.high.signed.v8i16(
@@ -286,9 +286,9 @@
 }
 
 ; CHECK-LABEL: extmul_low_u_v8i16:
-; SIMD128-NEXT: .functype extmul_low_u_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extmul_low_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_u_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extmul_low_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extmul.low.unsigned.v8i16(<16 x i8>, <16 x i8>)
 define <8 x i16> @extmul_low_u_v8i16(<16 x i8> %x, <16 x i8> %y) {
   %a = call <8 x i16> @llvm.wasm.extmul.low.unsigned.v8i16(
@@ -298,9 +298,9 @@
 }
 
 ; CHECK-LABEL: extmul_high_u_v8i16:
-; SIMD128-NEXT: .functype extmul_high_u_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extmul_high_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_u_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extmul_high_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extmul.high.unsigned.v8i16(<16 x i8>, <16 x i8>)
 define <8 x i16> @extmul_high_u_v8i16(<16 x i8> %x, <16 x i8> %y) {
   %a = call <8 x i16> @llvm.wasm.extmul.high.unsigned.v8i16(
@@ -310,9 +310,9 @@
 }
 
 ; CHECK-LABEL: extadd_pairwise_s_v8i16:
-; SIMD128-NEXT: .functype extadd_pairwise_s_v8i16 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extadd_pairwise_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extadd_pairwise_s_v8i16 (v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8>)
 define <8 x i16> @extadd_pairwise_s_v8i16(<16 x i8> %x) {
   %a = call <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8> %x)
@@ -320,9 +320,9 @@
 }
 
 ; CHECK-LABEL: extadd_pairwise_u_v8i16:
-; SIMD128-NEXT: .functype extadd_pairwise_u_v8i16 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extadd_pairwise_i8x16_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extadd_pairwise_u_v8i16 (v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8>)
 define <8 x i16> @extadd_pairwise_u_v8i16(<16 x i8> %x) {
   %a = call <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8> %x)
@@ -330,9 +330,9 @@
 }
 
 ; CHECK-LABEL: any_v8i16:
-; SIMD128-NEXT: .functype any_v8i16 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v8i16 (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>)
 define i32 @any_v8i16(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
@@ -340,9 +340,9 @@
 }
 
 ; CHECK-LABEL: all_v8i16:
-; SIMD128-NEXT: .functype all_v8i16 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v8i16 (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>)
 define i32 @all_v8i16(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
@@ -350,9 +350,9 @@
 }
 
 ; CHECK-LABEL: bitmask_v8i16:
-; SIMD128-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>)
 define i32 @bitmask_v8i16(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x)
@@ -360,9 +360,9 @@
 }
 
 ; CHECK-LABEL: bitselect_v8i16:
-; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
 define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) {
   %a = call <8 x i16> @llvm.wasm.bitselect.v8i16(
@@ -372,9 +372,9 @@
 }
 
 ; CHECK-LABEL: signselect_v8i16:
-; SIMD128-NEXT: .functype signselect_v8i16 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype signselect_v8i16 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.signselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
 define <8 x i16> @signselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) {
   %a = call <8 x i16> @llvm.wasm.signselect.v8i16(
@@ -384,9 +384,9 @@
 }
 
 ; CHECK-LABEL: narrow_signed_v8i16:
-; SIMD128-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>)
 define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) {
   %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(
@@ -396,9 +396,9 @@
 }
 
 ; CHECK-LABEL: narrow_unsigned_v8i16:
-; SIMD128-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>)
 define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) {
   %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(
@@ -411,9 +411,9 @@
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: dot:
-; SIMD128-NEXT: .functype dot (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype dot (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.dot(<8 x i16>, <8 x i16>)
 define <4 x i32> @dot(<8 x i16> %x, <8 x i16> %y) {
   %a = call <4 x i32> @llvm.wasm.dot(<8 x i16> %x, <8 x i16> %y)
@@ -422,9 +422,9 @@
 
 
 ; CHECK-LABEL: extmul_low_s_v4i32:
-; SIMD128-NEXT: .functype extmul_low_s_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extmul_low_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_s_v4i32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extmul_low_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extmul.low.signed.v4i32(<8 x i16>, <8 x i16>)
 define <4 x i32> @extmul_low_s_v4i32(<8 x i16> %x, <8 x i16> %y) {
   %a = call <4 x i32> @llvm.wasm.extmul.low.signed.v4i32(
@@ -434,9 +434,9 @@
 }
 
 ; CHECK-LABEL: extmul_high_s_v4i32:
-; SIMD128-NEXT: .functype extmul_high_s_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extmul_high_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_s_v4i32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extmul_high_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extmul.high.signed.v4i32(<8 x i16>, <8 x i16>)
 define <4 x i32> @extmul_high_s_v4i32(<8 x i16> %x, <8 x i16> %y) {
   %a = call <4 x i32> @llvm.wasm.extmul.high.signed.v4i32(
@@ -446,9 +446,9 @@
 }
 
 ; CHECK-LABEL: extmul_low_u_v4i32:
-; SIMD128-NEXT: .functype extmul_low_u_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extmul_low_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_u_v4i32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extmul_low_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extmul.low.unsigned.v4i32(<8 x i16>, <8 x i16>)
 define <4 x i32> @extmul_low_u_v4i32(<8 x i16> %x, <8 x i16> %y) {
   %a = call <4 x i32> @llvm.wasm.extmul.low.unsigned.v4i32(
@@ -458,9 +458,9 @@
 }
 
 ; CHECK-LABEL: extmul_high_u_v4i32:
-; SIMD128-NEXT: .functype extmul_high_u_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extmul_high_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_u_v4i32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extmul_high_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extmul.high.unsigned.v4i32(<8 x i16>, <8 x i16>)
 define <4 x i32> @extmul_high_u_v4i32(<8 x i16> %x, <8 x i16> %y) {
   %a = call <4 x i32> @llvm.wasm.extmul.high.unsigned.v4i32(
@@ -470,9 +470,9 @@
 }
 
 ; CHECK-LABEL: extadd_pairwise_s_v4i32:
-; SIMD128-NEXT: .functype extadd_pairwise_s_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extadd_pairwise_i16x8_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extadd_pairwise_s_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16>)
 define <4 x i32> @extadd_pairwise_s_v4i32(<8 x i16> %x) {
   %a = call <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16> %x)
@@ -480,9 +480,9 @@
 }
 
 ; CHECK-LABEL: extadd_pairwise_u_v4i32:
-; SIMD128-NEXT: .functype extadd_pairwise_u_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extadd_pairwise_i16x8_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extadd_pairwise_u_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16>)
 define <4 x i32> @extadd_pairwise_u_v4i32(<8 x i16> %x) {
   %a = call <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16> %x)
@@ -491,9 +491,9 @@
 
 
 ; CHECK-LABEL: any_v4i32:
-; SIMD128-NEXT: .functype any_v4i32 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v4i32 (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>)
 define i32 @any_v4i32(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
@@ -501,9 +501,9 @@
 }
 
 ; CHECK-LABEL: all_v4i32:
-; SIMD128-NEXT: .functype all_v4i32 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v4i32 (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>)
 define i32 @all_v4i32(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)
@@ -511,9 +511,9 @@
 }
 
 ; CHECK-LABEL: bitmask_v4i32:
-; SIMD128-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>)
 define i32 @bitmask_v4i32(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x)
@@ -521,9 +521,9 @@
 }
 
 ; CHECK-LABEL: bitselect_v4i32:
-; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define <4 x i32> @bitselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) {
   %a = call <4 x i32> @llvm.wasm.bitselect.v4i32(
@@ -533,9 +533,9 @@
 }
 
 ; CHECK-LABEL: signselect_v4i32:
-; SIMD128-NEXT: .functype signselect_v4i32 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype signselect_v4i32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.signselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define <4 x i32> @signselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) {
   %a = call <4 x i32> @llvm.wasm.signselect.v4i32(
@@ -545,10 +545,10 @@
 }
 
 ; CHECK-LABEL: trunc_sat_s_v4i32:
-; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0
-; SIMD128-NEXT: return $pop[[R]]
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
 declare <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float>)
 define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) {
   %a = call <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float> %x)
@@ -556,10 +556,10 @@
 }
 
 ; CHECK-LABEL: trunc_sat_u_v4i32:
-; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0
-; SIMD128-NEXT: return $pop[[R]]
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
 declare <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float>)
 define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) {
   %a = call <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float> %x)
@@ -567,9 +567,9 @@
 }
 
 ; CHECK-LABEL: trunc_sat_zero_signed_v4i32:
-; SIMD128-NEXT: .functype trunc_sat_zero_signed_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype trunc_sat_zero_signed_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.trunc.saturate.zero.signed(<2 x double>)
 define <4 x i32> @trunc_sat_zero_signed_v4i32(<2 x double> %a) {
   %v = call <4 x i32> @llvm.wasm.trunc.saturate.zero.signed(<2 x double> %a)
@@ -577,9 +577,9 @@
 }
 
 ; CHECK-LABEL: trunc_sat_zero_unsigned_v4i32:
-; SIMD128-NEXT: .functype trunc_sat_zero_unsigned_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype trunc_sat_zero_unsigned_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double>)
 define <4 x i32> @trunc_sat_zero_unsigned_v4i32(<2 x double> %a) {
   %v = call <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double> %a)
@@ -588,9 +588,9 @@
 
 
 ; CHECK-LABEL: widen_signed_v4i32:
-; SIMD128-NEXT: .functype widen_signed_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.widen_i8x16_s $push[[R:[0-9]+]]=, $0, 1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_signed_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.widen_i8x16_s $push[[R:[0-9]+]]=, $0, 1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.widen.signed(<16 x i8>, i32 immarg)
 define <4 x i32> @widen_signed_v4i32(<16 x i8> %x) {
   %v = call <4 x i32> @llvm.wasm.widen.signed(<16 x i8> %x, i32 1)
@@ -598,9 +598,9 @@
 }
 
 ; CHECK-LABEL: widen_unsigned_v4i32:
-; SIMD128-NEXT: .functype widen_unsigned_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.widen_i8x16_u $push[[R:[0-9]+]]=, $0, 1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_unsigned_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.widen_i8x16_u $push[[R:[0-9]+]]=, $0, 1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.widen.unsigned(<16 x i8>, i32 immarg)
 define <4 x i32> @widen_unsigned_v4i32(<16 x i8> %x) {
   %v = call <4 x i32> @llvm.wasm.widen.unsigned(<16 x i8> %x, i32 1)
@@ -611,9 +611,9 @@
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: eq_v2i64:
-; SIMD128-NEXT: .functype eq_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype eq_v2i64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.eq(<2 x i64>, <2 x i64>)
 define <2 x i64> @eq_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = call <2 x i64> @llvm.wasm.eq(<2 x i64> %x, <2 x i64> %y)
@@ -621,9 +621,9 @@
 }
 
 ; CHECK-LABEL: widen_low_s_v2i64:
-; SIMD128-NEXT: .functype widen_low_s_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.widen_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_low_s_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.widen_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.widen.low.signed(<4 x i32>)
 define <2 x i64> @widen_low_s_v2i64(<4 x i32> %x) {
   %a = call <2 x i64> @llvm.wasm.widen.low.signed(<4 x i32> %x)
@@ -631,9 +631,9 @@
 }
 
 ; CHECK-LABEL: widen_high_s_v2i64:
-; SIMD128-NEXT: .functype widen_high_s_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.widen_high_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_high_s_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.widen_high_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.widen.high.signed(<4 x i32>)
 define <2 x i64> @widen_high_s_v2i64(<4 x i32> %x) {
   %a = call <2 x i64> @llvm.wasm.widen.high.signed(<4 x i32> %x)
@@ -641,9 +641,9 @@
 }
 
 ; CHECK-LABEL: widen_low_u_v2i64:
-; SIMD128-NEXT: .functype widen_low_u_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.widen_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_low_u_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.widen_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.widen.low.unsigned(<4 x i32>)
 define <2 x i64> @widen_low_u_v2i64(<4 x i32> %x) {
   %a = call <2 x i64> @llvm.wasm.widen.low.unsigned(<4 x i32> %x)
@@ -651,9 +651,9 @@
 }
 
 ; CHECK-LABEL: widen_high_u_v2i64:
-; SIMD128-NEXT: .functype widen_high_u_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.widen_high_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_high_u_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.widen_high_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32>)
 define <2 x i64> @widen_high_u_v2i64(<4 x i32> %x) {
   %a = call <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32> %x)
@@ -661,9 +661,9 @@
 }
 
 ; CHECK-LABEL: extmul_low_s_v2i64:
-; SIMD128-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.extmul.low.signed.v2i64(<4 x i32>, <4 x i32>)
 define <2 x i64> @extmul_low_s_v2i64(<4 x i32> %x, <4 x i32> %y) {
   %a = call <2 x i64> @llvm.wasm.extmul.low.signed.v2i64(
@@ -673,9 +673,9 @@
 }
 
 ; CHECK-LABEL: extmul_high_s_v2i64:
-; SIMD128-NEXT: .functype extmul_high_s_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.extmul_high_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_s_v2i64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extmul_high_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.extmul.high.signed.v2i64(<4 x i32>, <4 x i32>)
 define <2 x i64> @extmul_high_s_v2i64(<4 x i32> %x, <4 x i32> %y) {
   %a = call <2 x i64> @llvm.wasm.extmul.high.signed.v2i64(
@@ -685,9 +685,9 @@
 }
 
 ; CHECK-LABEL: extmul_low_u_v2i64:
-; SIMD128-NEXT: .functype extmul_low_u_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.extmul_low_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_u_v2i64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extmul_low_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.extmul.low.unsigned.v2i64(<4 x i32>, <4 x i32>)
 define <2 x i64> @extmul_low_u_v2i64(<4 x i32> %x, <4 x i32> %y) {
   %a = call <2 x i64> @llvm.wasm.extmul.low.unsigned.v2i64(
@@ -697,9 +697,9 @@
 }
 
 ; CHECK-LABEL: extmul_high_u_v2i64:
-; SIMD128-NEXT: .functype extmul_high_u_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.extmul_high_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_u_v2i64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extmul_high_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.extmul.high.unsigned.v2i64(<4 x i32>, <4 x i32>)
 define <2 x i64> @extmul_high_u_v2i64(<4 x i32> %x, <4 x i32> %y) {
   %a = call <2 x i64> @llvm.wasm.extmul.high.unsigned.v2i64(
@@ -709,9 +709,9 @@
 }
 
 ; CHECK-LABEL: any_v2i64:
-; SIMD128-NEXT: .functype any_v2i64 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v2i64 (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>)
 define i32 @any_v2i64(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
@@ -719,9 +719,9 @@
 }
 
 ; CHECK-LABEL: all_v2i64:
-; SIMD128-NEXT: .functype all_v2i64 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v2i64 (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>)
 define i32 @all_v2i64(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
@@ -729,9 +729,9 @@
 }
 
 ; CHECK-LABEL: bitmask_v2i64:
-; SIMD128-NEXT: .functype bitmask_v2i64 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.bitmask $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitmask_v2i64 (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.bitmask.v2i64(<2 x i64>)
 define i32 @bitmask_v2i64(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.bitmask.v2i64(<2 x i64> %x)
@@ -739,9 +739,9 @@
 }
 
 ; CHECK-LABEL: bitselect_v2i64:
-; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
 define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) {
   %a = call <2 x i64> @llvm.wasm.bitselect.v2i64(
@@ -751,9 +751,9 @@
 }
 
 ; CHECK-LABEL: signselect_v2i64:
-; SIMD128-NEXT: .functype signselect_v2i64 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype signselect_v2i64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.signselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
 define <2 x i64> @signselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) {
   %a = call <2 x i64> @llvm.wasm.signselect.v2i64(
@@ -766,9 +766,9 @@
 ; 4 x f32
 ; ==============================================================================
 ; CHECK-LABEL: bitselect_v4f32:
-; SIMD128-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>)
 define <4 x float> @bitselect_v4f32(<4 x float> %v1, <4 x float> %v2, <4 x float> %c) {
   %a = call <4 x float> @llvm.wasm.bitselect.v4f32(
@@ -778,9 +778,9 @@
 }
 
 ; CHECK-LABEL: pmin_v4f32:
-; SIMD128-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.pmin.v4f32(<4 x float>, <4 x float>)
 define <4 x float> @pmin_v4f32(<4 x float> %a, <4 x float> %b) {
   %v = call <4 x float> @llvm.wasm.pmin.v4f32(<4 x float> %a, <4 x float> %b)
@@ -788,9 +788,9 @@
 }
 
 ; CHECK-LABEL: pmax_v4f32:
-; SIMD128-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.pmax.v4f32(<4 x float>, <4 x float>)
 define <4 x float> @pmax_v4f32(<4 x float> %a, <4 x float> %b) {
   %v = call <4 x float> @llvm.wasm.pmax.v4f32(<4 x float> %a, <4 x float> %b)
@@ -798,9 +798,9 @@
 }
 
 ; CHECK-LABEL: ceil_v4f32:
-; SIMD128-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.ceil.v4f32(<4 x float>)
 define <4 x float> @ceil_v4f32(<4 x float> %a) {
   %v = call <4 x float> @llvm.wasm.ceil.v4f32(<4 x float> %a)
@@ -808,9 +808,9 @@
 }
 
 ; CHECK-LABEL: floor_v4f32:
-; SIMD128-NEXT: .functype floor_v4f32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype floor_v4f32 (v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.floor.v4f32(<4 x float>)
 define <4 x float> @floor_v4f32(<4 x float> %a) {
   %v = call <4 x float> @llvm.wasm.floor.v4f32(<4 x float> %a)
@@ -818,9 +818,9 @@
 }
 
 ; CHECK-LABEL: trunc_v4f32:
-; SIMD128-NEXT: .functype trunc_v4f32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype trunc_v4f32 (v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.trunc.v4f32(<4 x float>)
 define <4 x float> @trunc_v4f32(<4 x float> %a) {
   %v = call <4 x float> @llvm.wasm.trunc.v4f32(<4 x float> %a)
@@ -828,9 +828,9 @@
 }
 
 ; CHECK-LABEL: nearest_v4f32:
-; SIMD128-NEXT: .functype nearest_v4f32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype nearest_v4f32 (v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.nearest.v4f32(<4 x float>)
 define <4 x float> @nearest_v4f32(<4 x float> %a) {
   %v = call <4 x float> @llvm.wasm.nearest.v4f32(<4 x float> %a)
@@ -838,9 +838,9 @@
 }
 
 ; CHECK-LABEL: qfma_v4f32:
-; SIMD128-NEXT: .functype qfma_v4f32 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype qfma_v4f32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.qfma.v4f32(<4 x float>, <4 x float>, <4 x float>)
 define <4 x float> @qfma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
   %v = call <4 x float> @llvm.wasm.qfma.v4f32(
@@ -850,9 +850,9 @@
 }
 
 ; CHECK-LABEL: qfms_v4f32:
-; SIMD128-NEXT: .functype qfms_v4f32 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype qfms_v4f32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.qfms.v4f32(<4 x float>, <4 x float>, <4 x float>)
 define <4 x float> @qfms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
   %v = call <4 x float> @llvm.wasm.qfms.v4f32(
@@ -862,9 +862,9 @@
 }
 
 ; CHECK-LABEL: demote_zero_v4f32:
-; SIMD128-NEXT: .functype demote_zero_v4f32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.demote_zero_f64x2 $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype demote_zero_v4f32 (v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.demote_zero_f64x2 $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.demote.zero(<2 x double>)
 define <4 x float> @demote_zero_v4f32(<2 x double> %a) {
   %v = call <4 x float> @llvm.wasm.demote.zero(<2 x double> %a)
@@ -875,9 +875,9 @@
 ; 2 x f64
 ; ==============================================================================
 ; CHECK-LABEL: bitselect_v2f64:
-; SIMD128-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>)
 define <2 x double> @bitselect_v2f64(<2 x double> %v1, <2 x double> %v2, <2 x double> %c) {
   %a = call <2 x double> @llvm.wasm.bitselect.v2f64(
@@ -887,9 +887,9 @@
 }
 
 ; CHECK-LABEL: pmin_v2f64:
-; SIMD128-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.pmin.v2f64(<2 x double>, <2 x double>)
 define <2 x double> @pmin_v2f64(<2 x double> %a, <2 x double> %b) {
   %v = call <2 x double> @llvm.wasm.pmin.v2f64(<2 x double> %a, <2 x double> %b)
@@ -897,9 +897,9 @@
 }
 
 ; CHECK-LABEL: pmax_v2f64:
-; SIMD128-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.pmax.v2f64(<2 x double>, <2 x double>)
 define <2 x double> @pmax_v2f64(<2 x double> %a, <2 x double> %b) {
   %v = call <2 x double> @llvm.wasm.pmax.v2f64(<2 x double> %a, <2 x double> %b)
@@ -907,9 +907,9 @@
 }
 
 ; CHECK-LABEL: ceil_v2f64:
-; SIMD128-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.ceil.v2f64(<2 x double>)
 define <2 x double> @ceil_v2f64(<2 x double> %a) {
   %v = call <2 x double> @llvm.wasm.ceil.v2f64(<2 x double> %a)
@@ -917,9 +917,9 @@
 }
 
 ; CHECK-LABEL: floor_v2f64:
-; SIMD128-NEXT: .functype floor_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.floor $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype floor_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.floor $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.floor.v2f64(<2 x double>)
 define <2 x double> @floor_v2f64(<2 x double> %a) {
   %v = call <2 x double> @llvm.wasm.floor.v2f64(<2 x double> %a)
@@ -927,9 +927,9 @@
 }
 
 ; CHECK-LABEL: trunc_v2f64:
-; SIMD128-NEXT: .functype trunc_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.trunc $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype trunc_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.trunc $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.trunc.v2f64(<2 x double>)
 define <2 x double> @trunc_v2f64(<2 x double> %a) {
   %v = call <2 x double> @llvm.wasm.trunc.v2f64(<2 x double> %a)
@@ -937,9 +937,9 @@
 }
 
 ; CHECK-LABEL: nearest_v2f64:
-; SIMD128-NEXT: .functype nearest_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype nearest_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.nearest.v2f64(<2 x double>)
 define <2 x double> @nearest_v2f64(<2 x double> %a) {
   %v = call <2 x double> @llvm.wasm.nearest.v2f64(<2 x double> %a)
@@ -947,9 +947,9 @@
 }
 
 ; CHECK-LABEL: qfma_v2f64:
-; SIMD128-NEXT: .functype qfma_v2f64 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype qfma_v2f64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.qfma.v2f64(<2 x double>, <2 x double>, <2 x double>)
 define <2 x double> @qfma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
   %v = call <2 x double> @llvm.wasm.qfma.v2f64(
@@ -959,9 +959,9 @@
 }
 
 ; CHECK-LABEL: qfms_v2f64:
-; SIMD128-NEXT: .functype qfms_v2f64 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype qfms_v2f64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.qfms.v2f64(<2 x double>, <2 x double>, <2 x double>)
 define <2 x double> @qfms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
   %v = call <2 x double> @llvm.wasm.qfms.v2f64(
@@ -971,9 +971,9 @@
 }
 
 ; CHECK-LABEL: convert_low_signed_v2f64:
-; SIMD128-NEXT: .functype convert_low_signed_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.convert_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype convert_low_signed_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.convert_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.convert.low.signed(<4 x i32>)
 define <2 x double> @convert_low_signed_v2f64(<4 x i32> %a) {
   %v = call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %a)
@@ -981,9 +981,9 @@
 }
 
 ; CHECK-LABEL: convert_low_unsigned_v2f64:
-; SIMD128-NEXT: .functype convert_low_unsigned_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.convert_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype convert_low_unsigned_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.convert_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32>)
 define <2 x double> @convert_low_unsigned_v2f64(<4 x i32> %a) {
   %v = call <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32> %a)
@@ -991,9 +991,9 @@
 }
 
 ; CHECK-LABEL: promote_low_v2f64:
-; SIMD128-NEXT: .functype promote_low_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.promote_low_f32x4 $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype promote_low_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.promote_low_f32x4 $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.promote.low(<4 x float>)
 define <2 x double> @promote_low_v2f64(<4 x float> %a) {
   %v = call <2 x double> @llvm.wasm.promote.low(<4 x float> %a)
Index: llvm/test/CodeGen/WebAssembly/simd-conversions.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-conversions.ll
+++ llvm/test/CodeGen/WebAssembly/simd-conversions.ll
@@ -1,5 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that vector float-to-int and int-to-float instructions lower correctly
@@ -29,7 +28,7 @@
 
 ; CHECK-LABEL: convert_s_v2f64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: f64x2.convert_i64x2_s
+; SIMD128-NOT: f64x2.convert_i64x2_s
 ; SIMD128-NEXT: .functype convert_s_v2f64 (v128) -> (v128){{$}}
 define <2 x double> @convert_s_v2f64(<2 x i64> %x) {
   %a = sitofp <2 x i64> %x to <2 x double>
@@ -38,7 +37,7 @@
 
 ; CHECK-LABEL: convert_u_v2f64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: f64x2.convert_i64x2_u
+; SIMD128-NOT: f64x2.convert_i64x2_u
 ; SIMD128-NEXT: .functype convert_u_v2f64 (v128) -> (v128){{$}}
 define <2 x double> @convert_u_v2f64(<2 x i64> %x) {
   %a = uitofp <2 x i64> %x to <2 x double>
@@ -67,7 +66,7 @@
 
 ; CHECK-LABEL: trunc_sat_s_v2i64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: i64x2.trunc_sat_f64x2_s
+; SIMD128-NOT: i64x2.trunc_sat_f64x2_s
 ; SIMD128-NEXT: .functype trunc_sat_s_v2i64 (v128) -> (v128){{$}}
 define <2 x i64> @trunc_sat_s_v2i64(<2 x double> %x) {
   %a = fptosi <2 x double> %x to <2 x i64>
@@ -76,7 +75,7 @@
 
 ; CHECK-LABEL: trunc_sat_u_v2i64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: i64x2.trunc_sat_f64x2_u
+; SIMD128-NOT: i64x2.trunc_sat_f64x2_u
 ; SIMD128-NEXT: .functype trunc_sat_u_v2i64 (v128) -> (v128){{$}}
 define <2 x i64> @trunc_sat_u_v2i64(<2 x double> %x) {
   %a = fptoui <2 x double> %x to <2 x i64>
Index: llvm/test/CodeGen/WebAssembly/simd-comparisons.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-comparisons.ll
+++ llvm/test/CodeGen/WebAssembly/simd-comparisons.ll
@@ -1,5 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test SIMD comparison operators
Index: llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
+++ llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
@@ -1,5 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes=CHECK,UNIMP
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes=CHECK,SIMD-VM
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
 
 ; Test that the logic to choose between v128.const vector
 ; initialization and splat vector initialization and to optimize the
@@ -8,95 +7,11 @@
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
-; CHECK-LABEL:  emulated_const_trivial_splat:
-; CHECK-NEXT:   .functype       emulated_const_trivial_splat () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-; UNIMP: v128.const
-define <4 x i32> @emulated_const_trivial_splat() {
-  ret <4 x i32> <i32 1, i32 2, i32 1, i32 2>
-}
-
-; CHECK-LABEL:  emulated_const_first_sufficient:
-; CHECK-NEXT:   .functype       emulated_const_first_sufficient () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-; UNIMP: v128.const
-define <4 x i32> @emulated_const_first_sufficient() {
-  ret <4 x i32> <i32 1, i32 2, i32 undef, i32 2>
-}
-
-; CHECK-LABEL:  emulated_const_second_sufficient:
-; CHECK-NEXT:   .functype       emulated_const_second_sufficient () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-; UNIMP: v128.const
-define <4 x i32> @emulated_const_second_sufficient() {
-  ret <4 x i32> <i32 1, i32 undef, i32 1, i32 2>
-}
-
-; CHECK-LABEL:  emulated_const_combined_sufficient:
-; CHECK-NEXT:   .functype       emulated_const_combined_sufficient () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-; UNIMP: v128.const
-define <4 x i32> @emulated_const_combined_sufficient() {
-  ret <4 x i32> <i32 1, i32 undef, i32 undef, i32 2>
-}
-
-; CHECK-LABEL:  emulated_const_either_sufficient:
-; CHECK-NEXT:   .functype       emulated_const_either_sufficient () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 1
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-; UNIMP: v128.const
-define <4 x i32> @emulated_const_either_sufficient() {
-  ret <4 x i32> <i32 1, i32 undef, i32 1, i32 undef>
-}
-
-; CHECK-LABEL: emulated_const_neither_sufficient:
-; CHECK-NEXT:   .functype       emulated_const_neither_sufficient () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: i64.const       $push2=, 17179869184
-; SIMD-VM-NEXT: i64x2.replace_lane      $push3=, $pop1, 1, $pop2
-; SIMD-VM-NEXT: return  $pop3
-define <4 x i32> @emulated_const_neither_sufficient() {
-  ret <4 x i32> <i32 1, i32 2, i32 undef, i32 4>
-}
-
-; CHECK-LABEL:  emulated_const_combined_sufficient_large:
-; CHECK-NEXT:   .functype       emulated_const_combined_sufficient_large () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 506097522914230528
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-define <16 x i8> @emulated_const_combined_sufficient_large() {
-  ret <16 x i8> <i8 0, i8 undef, i8 2, i8 undef, i8 4, i8 undef, i8 6, i8 undef,
-                 i8 undef, i8 1, i8 undef, i8 3, i8 undef, i8 5, i8 undef, i8 7>
-}
-
-; CHECK-LABEL: emulated_const_neither_sufficient_large:
-; CHECK-NEXT:   .functype       emulated_const_neither_sufficient_large () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, -70368726997663744
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: i64.const       $push2=, 504408655873966336
-; SIMD-VM-NEXT: i64x2.replace_lane      $push3=, $pop1, 1, $pop2
-; SIMD-VM-NEXT: return  $pop3
-define <16 x i8> @emulated_const_neither_sufficient_large() {
-  ret <16 x i8> <i8 0, i8 undef, i8 2, i8 undef, i8 4, i8 undef, i8 6, i8 255,
-                 i8 undef, i8 1, i8 undef, i8 3, i8 undef, i8 5, i8 undef, i8 7>
-}
-
 ; CHECK-LABEL: same_const_one_replaced_i16x8:
 ; CHECK-NEXT:  .functype       same_const_one_replaced_i16x8 (i32) -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 42, 42, 42, 42, 42, 0, 42, 42
-; UNIMP-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
-; UNIMP-NEXT:  return          $pop[[L1]]
-; SIMD-VM: i64x2.splat
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 42, 42, 42, 42, 42, 0, 42, 42
+; CHECK-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
+; CHECK-NEXT:  return          $pop[[L1]]
 define <8 x i16> @same_const_one_replaced_i16x8(i16 %x) {
   %v = insertelement
     <8 x i16> <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>,
@@ -107,10 +22,9 @@
 
 ; CHECK-LABEL: different_const_one_replaced_i16x8:
 ; CHECK-NEXT:  .functype       different_const_one_replaced_i16x8 (i32) -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 1, -2, 3, -4, 5, 0, 7, -8
-; UNIMP-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
-; UNIMP-NEXT:  return          $pop[[L1]]
-; SIMD-VM: i64x2.splat
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 1, -2, 3, -4, 5, 0, 7, -8
+; CHECK-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
+; CHECK-NEXT:  return          $pop[[L1]]
 define <8 x i16> @different_const_one_replaced_i16x8(i16 %x) {
   %v = insertelement
     <8 x i16> <i16 1, i16 -2, i16 3, i16 -4, i16 5, i16 -6, i16 7, i16 -8>,
@@ -121,10 +35,9 @@
 
 ; CHECK-LABEL: same_const_one_replaced_f32x4:
 ; CHECK-NEXT:  .functype       same_const_one_replaced_f32x4 (f32) -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x1.5p5, 0x1.5p5, 0x0p0, 0x1.5p5
-; UNIMP-NEXT:  f32x4.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 2, $0
-; UNIMP-NEXT:  return          $pop[[L1]]
-; SIMD-VM: f32x4.splat
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x1.5p5, 0x1.5p5, 0x0p0, 0x1.5p5
+; CHECK-NEXT:  f32x4.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 2, $0
+; CHECK-NEXT:  return          $pop[[L1]]
 define <4 x float> @same_const_one_replaced_f32x4(float %x) {
   %v = insertelement
     <4 x float> <float 42., float 42., float 42., float 42.>,
@@ -135,10 +48,9 @@
 
 ; CHECK-LABEL: different_const_one_replaced_f32x4:
 ; CHECK-NEXT:  .functype       different_const_one_replaced_f32x4 (f32) -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x1p0, 0x1p1, 0x0p0, 0x1p2
-; UNIMP-NEXT:  f32x4.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 2, $0
-; UNIMP-NEXT:  return          $pop[[L1]]
-; SIMD-VM: f32x4.splat
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x1p0, 0x1p1, 0x0p0, 0x1p2
+; CHECK-NEXT:  f32x4.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 2, $0
+; CHECK-NEXT:  return          $pop[[L1]]
 define <4 x float> @different_const_one_replaced_f32x4(float %x) {
   %v = insertelement
     <4 x float> <float 1., float 2., float 3., float 4.>,
@@ -149,9 +61,8 @@
 
 ; CHECK-LABEL: splat_common_const_i32x4:
 ; CHECK-NEXT:  .functype       splat_common_const_i32x4 () -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0, 3, 3, 1
-; UNIMP-NEXT:  return          $pop[[L0]]
-; SIMD-VM: i64x2.splat
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0, 3, 3, 1
+; CHECK-NEXT:  return          $pop[[L0]]
 define <4 x i32> @splat_common_const_i32x4() {
   ret <4 x i32> <i32 undef, i32 3, i32 3, i32 1>
 }
@@ -284,12 +195,11 @@
 
 ; CHECK-LABEL: mashup_const_i8x16:
 ; CHECK-NEXT:  .functype       mashup_const_i8x16 (v128, v128, i32) -> (v128)
-; UNIMP:       v128.const      $push[[L0:[0-9]+]]=, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 0
-; UNIMP:       i8x16.replace_lane
-; UNIMP:       i8x16.replace_lane
-; UNIMP:       i8x16.replace_lane
-; UNIMP:       return
-; SIMD-VM: i64x2.splat
+; CHECK:       v128.const      $push[[L0:[0-9]+]]=, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 0
+; CHECK:       i8x16.replace_lane
+; CHECK:       i8x16.replace_lane
+; CHECK:       i8x16.replace_lane
+; CHECK:       return
 define <16 x i8> @mashup_const_i8x16(<16 x i8> %src, <16 x i8> %mask, i8 %splatted) {
   ; swizzle 0
   %m0 = extractelement <16 x i8> %mask, i32 0
@@ -328,8 +238,8 @@
 
 ; CHECK-LABEL: undef_const_insert_f32x4:
 ; CHECK-NEXT:  .functype       undef_const_insert_f32x4 () -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x0p0, 0x1.5p5, 0x0p0, 0x0p0
-; UNIMP-NEXT:  return          $pop[[L0]]
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x0p0, 0x1.5p5, 0x0p0, 0x0p0
+; CHECK-NEXT:  return          $pop[[L0]]
 ; SIMD-VM: f32x4.splat
 define <4 x float> @undef_const_insert_f32x4() {
   %v = insertelement <4 x float> undef, float 42., i32 1
Index: llvm/test/CodeGen/WebAssembly/simd-arith.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/simd-arith.ll
+++ llvm/test/CodeGen/WebAssembly/simd-arith.ll
@@ -1,13 +1,14 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
+
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
+
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; check that a non-test run (including explicit locals pass) at least finishes
-; RUN: llc < %s -O0 -mattr=+unimplemented-simd128
-; RUN: llc < %s -O2 -mattr=+unimplemented-simd128
+; RUN: llc < %s -O0 -mattr=+simd128
+; RUN: llc < %s -O2 -mattr=+simd128
 
 ; Test that basic SIMD128 arithmetic operations assemble as expected.
 
Index: llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
===================================================================
--- llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1702,16 +1702,14 @@
   std::function<bool(size_t, const SDValue &)> IsLaneConstructed;
   SDValue Result;
   // Prefer swizzles over vector consts over splats
-  if (NumSwizzleLanes >= NumSplatLanes && NumSwizzleLanes >= NumConstantLanes)) {
+  if (NumSwizzleLanes >= NumSplatLanes && NumSwizzleLanes >= NumConstantLanes) {
     Result = DAG.getNode(WebAssemblyISD::SWIZZLE, DL, VecT, SwizzleSrc,
                          SwizzleIndices);
     auto Swizzled = std::make_pair(SwizzleSrc, SwizzleIndices);
     IsLaneConstructed = [&, Swizzled](size_t I, const SDValue &Lane) {
       return Swizzled == GetSwizzleSrcs(I, Lane);
     };
-    }
-  else if (NumConstantLanes >= NumSplatLanes) {
-    // If we support v128.const, emit it directly
+  } else if (NumConstantLanes >= NumSplatLanes) {
     SmallVector<SDValue, 16> ConstLanes;
     for (const SDValue &Lane : Op->op_values()) {
       if (IsConstant(Lane)) {
@@ -1726,55 +1724,6 @@
     IsLaneConstructed = [&IsConstant](size_t _, const SDValue &Lane) {
       return IsConstant(Lane);
     };
-  } else if (NumConstantLanes >= NumSplatLanes && VecT.isInteger()) {
-    // Otherwise, if this is an integer vector, pack the lane values together so
-    // we can construct the 128-bit constant from a pair of i64s using a splat
-    // followed by at most one i64x2.replace_lane. Also keep track of the lanes
-    // that actually matter so we can avoid the replace_lane in more cases.
-    std::array<uint64_t, 2> I64s{{0, 0}};
-    std::array<uint64_t, 2> ConstLaneMasks{{0, 0}};
-    size_t LaneBits = 128 / Lanes;
-    size_t HalfLanes = Lanes / 2;
-    for (size_t I = 0; I < Lanes; ++I) {
-      const SDValue &Lane = Op.getOperand(I);
-      if (IsConstant(Lane)) {
-        // How much we need to shift Val to position it in an i64
-        auto Shift = LaneBits * (I % HalfLanes);
-        auto Mask = maskTrailingOnes<uint64_t>(LaneBits);
-        auto Val = cast<ConstantSDNode>(Lane.getNode())->getZExtValue() & Mask;
-        I64s[I / HalfLanes] |= Val << Shift;
-        ConstLaneMasks[I / HalfLanes] |= Mask << Shift;
-      }
-    }
-    // Check whether all constant lanes in the second half of the vector are
-    // equivalent in the first half or vice versa to determine whether splatting
-    // either side will be sufficient to materialize the constant. As a special
-    // case, if the first and second halves have no constant lanes in common, we
-    // can just combine them.
-    bool FirstHalfSufficient = (I64s[0] & ConstLaneMasks[1]) == I64s[1];
-    bool SecondHalfSufficient = (I64s[1] & ConstLaneMasks[0]) == I64s[0];
-    bool CombinedSufficient = (ConstLaneMasks[0] & ConstLaneMasks[1]) == 0;
-
-    uint64_t Splatted;
-    if (SecondHalfSufficient) {
-      Splatted = I64s[1];
-    } else if (CombinedSufficient) {
-      Splatted = I64s[0] | I64s[1];
-    } else {
-      Splatted = I64s[0];
-    }
-
-    Result = DAG.getSplatBuildVector(MVT::v2i64, DL,
-                                     DAG.getConstant(Splatted, DL, MVT::i64));
-    if (!FirstHalfSufficient && !SecondHalfSufficient && !CombinedSufficient) {
-      Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, MVT::v2i64, Result,
-                           DAG.getConstant(I64s[1], DL, MVT::i64),
-                           DAG.getConstant(1, DL, MVT::i32));
-    }
-    Result = DAG.getBitcast(VecT, Result);
-    IsLaneConstructed = [&IsConstant](size_t _, const SDValue &Lane) {
-      return IsConstant(Lane);
-    };
   } else {
     // Use a splat, but possibly a load_splat
     LoadSDNode *SplattedLoad;
Index: clang/test/Preprocessor/wasm-target-features.c
===================================================================
--- clang/test/Preprocessor/wasm-target-features.c
+++ clang/test/Preprocessor/wasm-target-features.c
@@ -7,15 +7,6 @@
 //
 // SIMD128:#define __wasm_simd128__ 1{{$}}
 
-// RUN: %clang -E -dM %s -o - 2>&1 \
-// RUN:     -target wasm32-unknown-unknown -munimplemented-simd128 \
-// RUN:   | FileCheck %s -check-prefix=SIMD128-UNIMPLEMENTED
-// RUN: %clang -E -dM %s -o - 2>&1 \
-// RUN:     -target wasm64-unknown-unknown -munimplemented-simd128 \
-// RUN:   | FileCheck %s -check-prefix=SIMD128-UNIMPLEMENTED
-//
-// SIMD128-UNIMPLEMENTED:#define __wasm_unimplemented_simd128__ 1{{$}}
-
 // RUN: %clang -E -dM %s -o - 2>&1 \
 // RUN:     -target wasm32-unknown-unknown -mnontrapping-fptoint \
 // RUN:   | FileCheck %s -check-prefix=NONTRAPPING-FPTOINT
@@ -114,7 +105,6 @@
 // RUN:   | FileCheck %s -check-prefix=MVP
 //
 // MVP-NOT:#define __wasm_simd128__
-// MVP-NOT:#define __wasm_unimplemented_simd128__
 // MVP-NOT:#define __wasm_nontrapping_fptoint__
 // MVP-NOT:#define __wasm_sign_ext__
 // MVP-NOT:#define __wasm_exception_handling__
Index: clang/test/CodeGen/builtins-wasm.c
===================================================================
--- clang/test/CodeGen/builtins-wasm.c
+++ clang/test/CodeGen/builtins-wasm.c
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -triple wasm32-unknown-unknown -target-feature +unimplemented-simd128 -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY32
-// RUN: %clang_cc1 -triple wasm64-unknown-unknown -target-feature +unimplemented-simd128 -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY64
+// RUN: %clang_cc1 -triple wasm32-unknown-unknown -target-feature +simd128 -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY32
+// RUN: %clang_cc1 -triple wasm64-unknown-unknown -target-feature +simd128 -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY64
 // RUN: not %clang_cc1 -triple wasm64-unknown-unknown -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s 2>&1 | FileCheck %s -check-prefixes MISSING-SIMD
 
 // SIMD convenience types
@@ -884,34 +884,6 @@
   // WEBASSEMBLY: ret
 }
 
-f32x4 qfma_f32x4(f32x4 a, f32x4 b, f32x4 c) {
-  return __builtin_wasm_qfma_f32x4(a, b, c);
-  // WEBASSEMBLY: call <4 x float> @llvm.wasm.qfma.v4f32(
-  // WEBASSEMBLY-SAME: <4 x float> %a, <4 x float> %b, <4 x float> %c)
-  // WEBASSEMBLY-NEXT: ret
-}
-
-f32x4 qfms_f32x4(f32x4 a, f32x4 b, f32x4 c) {
-  return __builtin_wasm_qfms_f32x4(a, b, c);
-  // WEBASSEMBLY: call <4 x float> @llvm.wasm.qfms.v4f32(
-  // WEBASSEMBLY-SAME: <4 x float> %a, <4 x float> %b, <4 x float> %c)
-  // WEBASSEMBLY-NEXT: ret
-}
-
-f64x2 qfma_f64x2(f64x2 a, f64x2 b, f64x2 c) {
-  return __builtin_wasm_qfma_f64x2(a, b, c);
-  // WEBASSEMBLY: call <2 x double> @llvm.wasm.qfma.v2f64(
-  // WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b, <2 x double> %c)
-  // WEBASSEMBLY-NEXT: ret
-}
-
-f64x2 qfms_f64x2(f64x2 a, f64x2 b, f64x2 c) {
-  return __builtin_wasm_qfms_f64x2(a, b, c);
-  // WEBASSEMBLY: call <2 x double> @llvm.wasm.qfms.v2f64(
-  // WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b, <2 x double> %c)
-  // WEBASSEMBLY-NEXT: ret
-}
-
 i32x4 trunc_saturate_s_i32x4_f32x4(f32x4 f) {
   return __builtin_wasm_trunc_saturate_s_i32x4_f32x4(f);
   // WEBASSEMBLY: call <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float> %f)
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -17278,29 +17278,6 @@
     Function *Callee = CGM.getIntrinsic(Intrinsic::sqrt, Vec->getType());
     return Builder.CreateCall(Callee, {Vec});
   }
-  case WebAssembly::BI__builtin_wasm_qfma_f32x4:
-  case WebAssembly::BI__builtin_wasm_qfms_f32x4:
-  case WebAssembly::BI__builtin_wasm_qfma_f64x2:
-  case WebAssembly::BI__builtin_wasm_qfms_f64x2: {
-    Value *A = EmitScalarExpr(E->getArg(0));
-    Value *B = EmitScalarExpr(E->getArg(1));
-    Value *C = EmitScalarExpr(E->getArg(2));
-    unsigned IntNo;
-    switch (BuiltinID) {
-    case WebAssembly::BI__builtin_wasm_qfma_f32x4:
-    case WebAssembly::BI__builtin_wasm_qfma_f64x2:
-      IntNo = Intrinsic::wasm_qfma;
-      break;
-    case WebAssembly::BI__builtin_wasm_qfms_f32x4:
-    case WebAssembly::BI__builtin_wasm_qfms_f64x2:
-      IntNo = Intrinsic::wasm_qfms;
-      break;
-    default:
-      llvm_unreachable("unexpected builtin ID");
-    }
-    Function *Callee = CGM.getIntrinsic(IntNo, A->getType());
-    return Builder.CreateCall(Callee, {A, B, C});
-  }
   case WebAssembly::BI__builtin_wasm_narrow_s_i8x16_i16x8:
   case WebAssembly::BI__builtin_wasm_narrow_u_i8x16_i16x8:
   case WebAssembly::BI__builtin_wasm_narrow_s_i16x8_i32x4:
Index: clang/include/clang/Driver/Options.td
===================================================================
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3107,8 +3107,6 @@
   HelpText<"Select straight-line speculation hardening scope">;
 
 def msimd128 : Flag<["-"], "msimd128">, Group<m_wasm_Features_Group>;
-def munimplemented_simd128 : Flag<["-"], "munimplemented-simd128">, Group<m_wasm_Features_Group>;
-def mno_unimplemented_simd128 : Flag<["-"], "mno-unimplemented-simd128">, Group<m_wasm_Features_Group>;
 def mno_simd128 : Flag<["-"], "mno-simd128">, Group<m_wasm_Features_Group>;
 def mnontrapping_fptoint : Flag<["-"], "mnontrapping-fptoint">, Group<m_wasm_Features_Group>;
 def mno_nontrapping_fptoint : Flag<["-"], "mno-nontrapping-fptoint">, Group<m_wasm_Features_Group>;

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[PATCH] D98457: [WebAssembly] Remove unimplemented-simd target features

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